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The Dig Log Pixel

The presentation for the master thesis project
by

Chenghan Li

on 6 October 2013

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Transcript of The Dig Log Pixel

The charge injection from the switch makes VP curvy in the beginning.
Reset
VD
VP
Design of a Wide Dynamic Range Image Sensor with Digital Logarithmic Pixels
Master Thesis Defense
Neural Systems and Computation
Chenghan Li
Supervisor: Prof. Tobi Delbruck
29 Aug 2012
Institute of Neuroinformatics
"The DigLogPixel"
Inspiration
Outline
Fact: The human eye has a dynamic range of 120dB (10^6)
Fact: A high end digital camera has a dynamic range of 70dB (10^3~10^4)
“An SoC combining a 132 dB QVGA pixel array and a 32b DSP/MCU processor for vision applications” by CSEM, Neuchâtel, Switzerland
Problems
Conclusion
Solutions
The CSEM Pixel
The DigLogPixel
0.18um 1P6M
14um by 14um
29.23um by 29.23um
20%
10bit
Analog 3.3V, Digital 1.8V
59nW (30fps)
34nW (Simulated)
Technology
Pixel Size
Fill Factor
A/D Resolution
Supply Voltage
Power Consumption
Analog 3.3V, Digital 1.8V
0.18um 1P6M
20%
10bit
Make the pixel more compact
Acknowledgment
Tobi Delbruck
Shih-Chii Liu
Raphael Berner
Minhao Yang
Christian Braendly
Hesham Elsayd
Junseok Kim
&
Fellow NSC students
Thank you!
Logarithmic conversion & analog-to-digital conversion at the same time, within each individual pixel: fast random access to individual pixel output
The comparator is non-standard and asymmetrical. MN1 and MN3 share gate voltage with VD.
The complementary gate has little effect on VD. VP has a very linear start of integration.
The gate-drain capacitance of MN3 will transfer changes in V1 to VD.
As VD is pulled up, integration will slow down, the pulse will be delayed
A micrograph of the CSEM SoC
Future Development
UMC 0.18um Technology with 1 poly-silicon layer and 6 metal layers
The logarithmic counter is implemented with an off-chip complex programmable logic device (CPLD)
Compatible with the dynamic vision sensor (DVS a.k.a. Silicon Retina) developed by the sensor group: DVS senses temporal brightness changes logarithmically and has digital output.
Under-exposed*
Over-exposed*
Logarithmically encoded*
* Pictures adapated from: P.-F. Ruedi et al, "An SoC combining a 132dB QVGA Pixel Array and a 32b DSP/MCU processor for vision applications"
Simplified
Timing diagram with 2 examples
A single NMOS is used as the transmission gate.
The gate-source capacitance of MN5 transfers the change of Reset to VD, pushing VD off balance by ~50mV.
Reset
VD
VP
VP is inversely amplified from VD, and will have a very non-linear start of integration.
"Charge injection" from the switch makes the pulse come earlier than it should.
For a 4nA photocurrent, the pulse comes ~260ns earlier; (counter interval is 40ns)
For a 300fA photocurrent, the pulse comes ~3ms earlier. (counter interval is ~0.4ms)
The comparator is standard and symmetrical with the inclusion of MN2. VD is separated from the comparator.
The inclusion of MP6 makes a complementary transmission gate.
Block Diagram of the CSEM pixel
Reset
VP
VD
Analog part of the CSEM pixel circuit
Analog part of the DigLogPixel circuit
The chip borrowed pre-built components including a bias generator and a pad frame from a previous chip developed by our sensor group.
29um
29um
(~30% pixel area is unused)
3.2mm
1.5mm
176ns
V3
VP
Reference
VD
V1
V3
V1
VD
V3
141ns
VD
V1
The CSEM Pixel
The DigLogPixel
The CSEM Pixel
The DigLogPixel
V3
Reference
VP
Test and measurement in hardware
Integrate DigLogPixel with DVS
A photo of the PCB waiting to be assembled
4nA Photocurrent
4nA Photocurrent
Delay for 300fA
CSEM: 18us
DigLog: 10us
Architecture
Reset
VD
VD
Reset
nReset
VD
V1
Voltage (mV)
Time (us)
Time (us)
Voltage (mv)
Voltage (mV)
Voltage (mV)
Voltage (V)
Voltage (V)
Time (us)
Time (us)
Time (us)
Time (us)
Voltage (mV)
Voltage (mV)
Time (us)
Time (us)
(v)
(v)
(v)
30 by 60
Full transcript