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Computer Architecture & Organisation

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nizam kahar

on 7 March 2016

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Transcript of Computer Architecture & Organisation

Computer architecture is the conceptual design and fundamental operational structure of a computer system. It is the practical art of selecting and interconnecting hardware components to create computers that meet

cost goals.

Computer architecture is the design of the systems visible to the (assembly level) programmer or those
that have a direct impact on the logical execution of a program.
Instruction set,
Number of bits used for data representation (e.g., numbers, characters) ,
I/O mechanisms,
Addressing memory techniques.
Computer architecture & organisation


1. Students
attend all the subject lectures
2. Students who
to attend lectures without valid reasons are considered to have failed this subject (marks zero will be given)
- fill in the Student’s Leave Information Form
Mid-Term Test

Final Exam
Weighting CO1 CO2 CO3
10% 5% 5%
25% 15% 5% 5%
25% 15% 10%

40% 25% 15%
100% 60% 35% 5%
Practical (psycho motor)
Affective (soft skill)
quizes x5
Assignment x2
What is
computer architecture
• Almost every program that can run on an
original Pentium (or 8086) can run on a
Pentium 4.
• All computers in the Intel Pentium series
have the same architecture.
• Each version of the Pentium has a different
organization or implementation.
Same Architecture different Organization
Computer components
(or Microarchitecture) describes the data paths, data processing elements and data storage elements

Organization is how the architecture is implemented.
How much cache memory
Control signals,
interfaces between computer and peripherals,
memory technology being used.
What is
computer organisation
Computer Architecture?? Computer Organization??
-william stalling-
-william stalling-
The architecture does not change with different model, but its organization changes with changing technology.
The basic function of a computer
e.g., Input/Output (I/O)
Manage the computer resources and orchestrates the performance of its other functional parts
ability to store short-term
and long-term data
Four (4) types of operations
the computer can function as data movement device (a), transferring data or as strorage device (b), data processing involve storage data (c) and between stroage and external environment
internal structure of a computer
Central processing Unir (CPU):
controls the operation of the computer and performs its data processing functions (referred to as processor)
Main memory:
stores data
moves data between the computer and its external environment
System interconnection:
mechanism that provides for communication among CPU, main memory and I/O.
CPU structured components
Control unit:
controls the operation of the CPU and hence the computer
Arithmetic and logic unit (ALU):
Performs the computer's data processing functions.
provides storage internal to the CPU
CPU interconnection:
Some mechanism that provides for communication among the control unit, ALU, and registers.
Lesson outcomes: Understand the
basic of computer architecture
Number systems

Lesson outcomes: Able to perform operation on numbering system (i.e. binary, decimal and hexadecimal

Lesson outcomes:
define the bus systems
Communication pathway connecting two or more devices.
It is a
shared transmission
medium (allows connection to multiple devices). However, only
device can transmit data (or instruction) at a time.
Each line is capable of transmitting signals represent binary values (i.e. 1 or 0).
Hence, several lines of a bus can be used to transmit binary digits simultaneously (in parallel). For example: an 8-bit unit of data can be transmitted over eight bus lines.
The major parts of a computer model are the central processing unit (CPU), memory, and the Input and output circuitry (I/O).
Connecting these parts are 3 sets of parallel lines called buses.
These buses consists of 50 to 100 separate lines and each lines is assigned particular function.
The 3 buses are the
address bus
, the
data bus
, and the
control bus
It provide a
path for moving data between devices
Data bus may consist of from 32 to hundreds of separate lines (
= width
The number of lines (width) determine how many
bits can be transfered
at a time. This determine the overall
system performance
For example: if the data bus is 8 bits wide and each instruction is 16 bits long, the processor must access the memory module twice (2) during each instruction cycle.
The data bus lines are
NOTE: Many devices in a system will have their outputs connected to the data bus, but only one device at a time will have its outputs enabled.
Data Bus (or data line)

Used to
designate the source or destination of the data
on the data bus (
or address
of the address line determine
the maximum possible memory capacity of the system
. On these lines the CPU sends out the address of the memory location that is to be
written to or read from
. For example, if the processor want to read a word (8, 16 or 32 bits) of data from memory, it puts the address of the desired word on the address line.
The number of memory locations that the CPU can address is determined by the number of address lines. This is calculate using 2^N (or power(2,N)), for example: CPU with 16 address lines can address 65,536 memory (20 address line = ______ location?
NOTE: When the CPU reads data from or writes data to a port, it sends the port address out on the address bus.
Address Bus (or address lines)
Used to control the
access to and the use of the data and address lines
. Because data and address line are shared by all components, hence the control line act as mechanism to control their use.
The CPU sends out signals on the control bus to enable the outputs of addressed memory devices or port devices.
Typical control bus signals are;
Memory Read, Memory Write, I/O Read, and l/O Write, etc
Example: To read a byte of data from a memory location, the CPU sends out the memory address of the desired byte on the address bus and then sends out a Memory Read signal on the control bus. The Memory Read signal enables the addressed memory device to output a data word onto the data bus. The data word from memory travels along the data bus to the CPU.
Control Bus (control lines)
Lots of devices on one bus leads to:
Propagation delays
Long data paths mean that co-ordination of bus use can adversely affect performance
If aggregate data transfer approaches bus capacity
Most systems use
multiple buses
to overcome these problems
Bus Problems
Physical Realization
of Bus Architecture

Synchronous & Asynchronous
Elements of Bus design
System bus
Multiple buses
Traditional bus architecture
High-performace architecture
Dedicated bus:
There are separate wires for data and addresses
A store operation can put both the address and the data on the bus at the same time.
Having separate data and address lines simplifies the bus protocol
Dedicated & Multiplexed
Bus width:
Address & data
Transfer type:
Read-after-write, Block
Method of Arbitration:
Centralised & distributed
Multiplexed bus:
The same lines are used
at different times
to hold either data or addresses.
Multiplexed buses require fewer lines.
Chips can be limited in the number of pins that can be physically attached.
For a given number of pins, it is usually advantageous to transfer more data.
Data and addresses may appear on the bus at different times.
• Pentium is a 32-bit processor with a 64-bit data bus
• Itanium is a 64-bit processor with a 128-bit data bus
• Address bus width
– Determines the system addressing capacity
– N address lines directly address 2^N memory locations
• 8086: 20 address lines - able to address 1 MB of memory
• Pentium: 32 address lines - able to address 4 GB of memory
• Itanium: 64 address lines - able to address 264 Gbytes of memory
• AMD Athlon™ 64: 40 address lines - able to address 1 TB of memory
Example of bus width
What if more than one (1) module/devices need control of the bus? - 'arbiter'
a bus controller (arbiter) responsible for allocating time on the bus.
no central controller, whereby, each devices contains access control logic and the modules act together to share the bus.
Timing: refers to the way in which events are coordinated on the bus
synchronous timing: the occurence of events on the bus is determined by a clock.
asynchronous timing: the occurence of one event on a bus follows and depends on the occurence of a previous event.
width of the
data bus
has an impact on the system performance. The wider the data bus, the greater the number of bits transferred at one time.
width of address bus has an impact on system capacity. the wider the address bus, the greater the range of locations that can be referenced.
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