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DUCAT VLSI CONSULTANCY
Transcript of DUCAT VLSI CONSULTANCY
Phone : - 0120-4646464
Mobile: - +91- 9871055180
Responsibility Of VLSI Designer
Dr. Prabhu Goel In 1981 to join Wang Labs. In 1982 to start Gateway Design Automation which developed the now industry standard Verilog. He sold his stake at Gateway sold for about $80 million. He won the 2003 IEEE Industrial Pioneer Award for his work on design modeling and design verification through Verilog and Verilog-based design. He is now a private venture capitalist.
Gate Level Modeling
Data Flow Modeling
Switch level Modeling
module andgate( output y,input a,b );
Set Of Rules To Design A Chip
* Design Specification
* Behavioral Description
* RTL Description (HDL)
* Function Verification And Testing
* Logical Synthesis And Time Verification
* Gate Level Netlist
* Logical Verification And Testing
* Floor Planning Automatic Place and Route
* Physical Layout
* Layout Verification
Very Large Scale Integration
To Fabricate A Chip
reduced Power Consumption
Low In Cost
A process of investigating a design and demonstrating it to be accurate to specification.
A process which runs simultaneous to design creation process.
Verification as part of our daily routine:
Tasting a cuisine.
We even verify our thoughts.
An Engineer’s job
Interpret the design specification
Exercise tests on RTL
Making sure the tests signify the interpretation accurately
A Hardware Verification Language(HVL).
SystemVerilog is an extension of
IEEE 1364 Verilog-2001 standard.
It has features derived from Verilog,C,C++.
Directed testing detects the bugs you expect but Random testing detects the bugs you did not expect.
Automatic stimulus generation
Change the characteristics of the data driving the DUT
Random setting of parameters
Select ports, addresses, operational parameters randomly
A random test’s behavior depends on the seed
If you run the same test with the same seed, you will get the
If you run the same test with many different seeds, you will get
the equivalent of many different tests