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Network on Chip - A Journey Overview

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Sneha Ved

on 29 December 2013

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Transcript of Network on Chip - A Journey Overview

Background
Research Areas in NoCs
NoC is a marriage domain between networks and VLSI => pros from both the domains has converged, so has the cons
Since the networks are now in micrometer scale, the issues are similar, not the same
Shifted priorities
Shift in the mindset
Advent of Multi Cores
Network on Chip - A Journey Overview
Our Idea
A NoC design with asynch-sync hierarchy
A hybrid routing scheme of dimensional and adaptive routing
Memory Wall
Scaling of memory speed v/s processor speed
Techniques like memory hierarchy, pipelining memory accesses to handle the vast gap.
Handling very
deep memories and
heavy pipelining is getting tedious and unproductive
Frequency Wall
Not much scope to scale the transistor
Thermal management
Power to performance ratio deteriorating
Clocking massive chips
ILP Wall
Instruction Level Parallelism
Complete parallelization not possible
Cap on the benefits of adding excess cores
ILP overheads
Brick Wall
This combination of the Memory, Power and ILP wall that had baffled the architecture design community
Tricky balance act between conflicting goals
The industry was stunned when Intel cancelled not one but two premier processor designs in May of 2004. Intel's Tejas CPU2, Sanskrit for fire, dissipated a stupendous 150 watts at 2.8 GHz, more than Hasbro's Easy Bake Oven.

The Tejas had been projected to run 7 GHz. It never did. When microprocessors get too hot, they quit working and sometimes blow up.4
-
Russell Fish, EDN, November 17, 2011
We need to look for a drastically new design paradigm!
Multicore needs to be given a chance!
Multicore Design Paradigm
How different is it to think multicore?
What are the architecture domains that will need to undergo a make-over?
How does it relate to the activity in other domains in system design and applications?
Interconnect Design
Need for higher bandwidth
General Purpose
Multi-purpose
Scalable
Memory Management
Rethinking memory hierarchy
Shared or Distributed memory?
Accessibility and security
Flynn's Taxonomy
Cores
Simpler cores
Back to simple , shallow pipelining..rethinking OoO
Speculation overheads
Off the shelf, modular designs
Highly specialized, specific cores
BMW AutoSAR
ARM 11MPCORE
Intel Ne
ha
lem
Do we have any suitable interconnects available in VLSI?
Let's see what our alternatives are!
Soc Interconnects
Buses such as I2C, PCI, EISA, VGA, FireWire etc have been in industry for a long time
Time tested and successful in their market sector
Scalable?
AMBA2.0
De facto standard in the industry
One of the most flexible and customizable buses
Suited for wide range of applications from low power to high performance
Scalable?
Bandwidth?
Designing the interconnect based on Computer Networks
"Miniaturization" of computer networks
Highly flexible and scalable
Customizable
Can support high bandwidth requirements
Genesis of NoCs
Computer Networks
Concepts of establishing networks between the communicating parties
Algorithms
Analyses
Philosophy?
VLSI
Aims at maximum functionality per unit area
Brick Wall
Small is beautiful
Hard
Network on Chip
Micrometer Scaling of computer networks to function as on chip interconnects with the capabilities of a full fledged network
Advantages of both the parent fields and a new set of challenges
What does it involve?
The Union
NoC
VLSI
Computer Networks
Scaling
Power Management
Thermal Management
Buffer Management
Chip Real Estate
Delays, latencies and clocking
Topology
Routing
Flow and congestion control
Networking layers
NoC Topologies and Routing
Topology defines the physical layout of the network
Impact on minimum latency, wire length etc
Routing determines the path taken
Routing may be static or dynamic
Routing affects the buffer utilization, latency, logic etc.
A glance through some work done
Deflection based routing for bufferless design
Suitable for flit based and worm hole routing
Constraints on the topology
In this paper, the authors propose a scheme of reconfiguring the router at run time to optimize on power consumption.
In this paper, speculation on the input to the router is used to predict contention at the router and then "intelligently" select the input.
Interesting Research
Optical NoCs, Nanophotonic NoCs
Asynchronous Interconnects
Globally Asynchronous, Locally Synchronous Designs

This paper proposes a design of a GALS NoCs with enhanced power control
Neural NoC : SpiNNaker
AutoSAR : BMW's standard and system for automobiles
Intel Processors specification: WIkipedia
ARM 11MPCore: http://www.arm.com/products/processors/classic/arm11/arm11-mpcore.php
AutoSAR: http://www.autosar.org/
http://www.bit-tech.net/hardware/cpus/2008/11/03/intel-core-i7-nehalem-architecture-dive/5
http://www.phys.ncku.edu.tw/~htsu/humor/fry_egg.html
http://spectrum.ieee.org/computing/hardware/beat-the-heat
Patrick Gelsinger 2004, Roadmap to Computing
http://www.gotw.ca/publications/concurrency-ddj.htm
http://www.ict-ramplas.eu/Objectives.html
IITB VLSI Lab
FireWre Logo, Wikipedia
VLSI Lab IITB
D. R.; Plana L. A.; Rast A.; Jin X.; Painkras E.; Furber S. B Khan, M. M.; Lester. Spinnaker: Mapping neural networks onto a massively-parallel chip multiprocessor. In IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence)
http://de.m.wikipedia.org/wiki/Datei:Intel_Terascale_Tile_Arrangement.svg
Intel Terascale Architecture
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