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talking alarm clock

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by

imran asfar

on 23 November 2012

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Transcript of talking alarm clock

MSP430FG4618 has six operating modes
The operating modes mainly tackle three needs of a system:
Ultra low-power
Speed and data throughput
Minimization of individual peripheral current consumption
Turn off different clocks in different operating mode PRESENTATION LAYOUT Project Introduction
Experiments board and MSP430FG4618 microcontroller
System overview
A/D convertor and D/A convertor
Internal flash memory
TPA321 Power amplifier
Software design implementation
Basic timer/RTC module
Timer_B for A/D and D/A conversions
Low power mode
DMA controller operation SYSTEM OVERVIEW TALKING ALARM CLOCK
MSP430FG4618/F2013 EXPERIMENTS BOARD FLASH MEMORY CONTROLLER 116 KB flash memory
Segment erase and mass erase
Minimum VCC voltage during a flash write or erase operation is 2.7 V
Usage:
Program code and audio data stored in flash
Flash controller used for read/write access to the flash memory. DMA CONTROLLER Transfers data from one address to another, without CPU intervention.
Three independent transfer channels
Byte/word transfer capability
Configurable transfer trigger selection
Increase throughput of peripherals and decreases power consumption
Usage:
ADC module to flash memory transfer
Flash memory to DAC transfer 12 bit SAR ADC
Sample and hold controlled by timers or software
Conversion initiation by hardware timers
Usage:
To convert input from the microphone to digital audio. DAC MODULE 12 bit voltage output DAC
Resolution selection 8 or 12 bit
Can be used with DMA controller
Internal or external reference selection
Usage:
To convert digital audio data from flash memory to analogue sound. PROJECT INTRODUCTION Design and implementation of a talking alarm clock on a MSP430FG4618 experiments board

Low powered device ( 2xAAA cells)

Features personalized alarm message recording MSP430FG4618/F2013 Experiments board SOFTWARE BLOCK DIAGRAM SYSTEM OVERVIEW SOFTWARE IMPLEMENTAION ADC MODULE Low power mode operations(LPM) Low Power Modes Different low power mode disable different clocks

Peripherals operating with any disabled clock are disabled until the clock becomes active

Wake up is possible through all enabled interrupts
Returns to the previous operating mode if the status register value is not altered during the ISR MODES USED LPM0
CPU, MCLK off
DCO, SMCLK, ACLK on
LPM3
CPU, MCLK, DCO, SMCLK off
ACLK on

LPM 3 : Normal clock operation
LPM 0: During record, Playback and alarm

Stable SMCLK had to be used for peripherals Flash Memory Operation Read, write, erase mode
Default mode is read mode
Write/erase modes were selected with the WRT, MERAS, and ERASE bits

Flash Memory Timing Generator
Sourced from SMCLK
Must be in the range from ~ 257 kHz to ~ 476 kHz
Incorrect frequency may result in unpredictable write/erase operation
Flash timing generator Frequency was set to 333KHZ DMA Memory Transfers Recording:
Source address : ADC module
Destination address: Flash memory
Playback/Alarm:
Source address: Flash memory
Destination address: DAC module Flash memory sections DMA OPERATION
To overcome this issue, DMA channels were used in a chained fashion:

DMA0 reads/writes one block of flash memory
DMA1 loads the control register of DMA2
DMA2 reads/writes second block of flash memory TIMER_B 16 bit counter with three or seven capture control registers
Configurable output with PWM capabilities
Much more reliable than sofware generated counters .
Usage:
For automatic A/D and D/A conversions Flash memory sections Code memory 1( First block): 40 KB
Code memory 2 (Second block): 65 KB
Total of voice data memory: 105 KB Timer_B ( Initializing conversions) ADC ( Record routine)
Timer_B output triggers ADC12 conversion
ADC12IFG triggers DMA transfer
Repeat until memory full(DMASZ=0)
DAC (Alarm /Playback routine)
Timer_B output triggers DAC12 data latch
Timer_B CCIFG triggers DMA transfer
Repeat until whole memory read( DMASZ=0) Timer_B SETUP Timer_B used in UP mode
This sets up periodic outputs in hardware without software interference
The capture control registers configured to set the sampling frequency for ADC conversions
Sampling frequency set to 8.3 KHZ SUMMARY Alarm clock with LCD display and mode selection.
Alarm clock records 6 seconds of speech.
With total storage memory of 105 KB and ADC sampling frequency of about 8KHZ.
low powered device with a average current consumption of 31 uA .
Estimated battery life: 3-5 years Principles for Low-Power Applications Maximize the time in LPM3
Use interrupts to wake the processor and control program flow
Peripherals should be switched on only when needed

Use low-power integrated peripheral modules in place of software driven functions
For example: DMA

Using flash memory for storing software code and audio data. LEARNING OUTCOMES Flash memory usage Basic timer/RTC module RTC module operates the clock

It is controlled by the basic timer

Basic timer updates the display
Hours: Mins : Sec
Alarm comparison in basic timer ISR Driving an LCD display Displaying an adjustable clock on display
Full transcript