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Copy of LTE Physical Layer

A brief overview on the LTE Physical Layer

Ahmmed Shafi

on 19 February 2013

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Transcript of Copy of LTE Physical Layer

Presented By
Alkiviadis Zaganiaris Implementation of Transmitter & Receiver for an LTE-Advanced System What challenges do we face? #1 High ISI (Inter-Symbol-Interference) Final Year Project Implementation of Transmitter & Receiver for an LTE-A System Work Plan Semester 1
Document 3GPP series 36 rel.11
Physical Layer Report

Semester 2
Simulate DL-SCH & PDSCH using Simulink & Xilinx Sysgen Toolbox and perform analysis.
Use Xilinx IDE to port model onto Virtex 5 FPGA
Test design on ML505 Xilinx Evaluation board Tx - Rx Model 3GPP 36 Series - Rel.11 Next Stage
Simulate Model using
Simulink & Xilinx SysGen Toolbox Faster Data rates are proportional to a Symbol size decrease Effect: If path delay is larger than symbol size, ISI occurs. Cause: Multipath Propagation Path Delay: A signal can reach antennae from multiple paths and at slightly different phases. #2 IMT-Advanced Requirements Data Rate Requirements:
1 Gbps - Stationary users
100 Mbps - Normal Rate Target:
1. Develop Simulation of LTE-A system using Simulink & Xilinx SysGen Toolbox
2. Prepare comprehensive study of simulation model
3. Implement Design on Xilinx ML505 evaluation platform ML505 Applications: Data Transmission and Manipulation, Serial Connectivity, Digital Video, Bus Interface, High Speed Design Literature Review The two main concepts in Lit. Review were:
OFDM - Orthogonal Frequency Division Multiplexing
Increasing user capacity
Increasing Bandwidth Efficiency
Increasing data rates
OFDM Symbol Generation (IFFT/FFT)
Added CP (Cyclic Prefix)
MIMO - Multiple In Multiple Out
Increasing Bandwidth Efficiency
Combating Deep Channel Fading & Frequency Selective channels Simulink & Xilinx SysGen Toolbox Simulink
End-2-End simulation of model
Pre-coded Communication Blocksets
Program Parameters to match specifications
Analysis of model over time
BER Calculations
BLER Calculations

Xilinx SysGen Toolbox
Works in conjunction with Simulink
Provides pre-coded blocksets
Xilinx biased implementation
Easier translation of model into HDL
Xilinx ML505
Evaluation Platform Thank You

Any Questions? Some Useful Features:

Video Input/Output VGA interface
Multiple GPIO's
Rotary Encoder
JTAG programming Interface
Compact Flash Card
(Read input)

DL-SCH | PDSCH Expectations Weeks 1-4: Complete Simulation
Start Analysis Week 5-7: Port Design onto Virtex5
Learn to use ML505 Week 8-12: Program ML505 for
analytical purposes
Full transcript