Send the link below via email or IMCopy
Present to your audienceStart remote presentation
- Invited audience members will follow you as you navigate and present
- People invited to a presentation do not need a Prezi account
- This link expires 10 minutes after you close the presentation
- A maximum of 30 users can follow your presentation
- Learn more about this feature in our knowledge base article
Do you really want to delete this prezi?
Neither you, nor the coeditors you shared it with will be able to recover it again.
Make your likes visible on Facebook?
Connect your Facebook account to Prezi and let your likes appear on your timeline.
You can change this under Settings & Account at any time.
Transcript of Chameleon Chips
Technologies Used In Chip
Reconfigurable Processing Fabric(RPF)
A microprocessor adapting itself to the actual use and environment.
Machine design supposes that some pins are considered as the configuration inputs and another as data or control inputs and outputs.
A new chip must inside determine the set of the function blocks (FB), which are used to construct the circuit, rules of their interconnections and ways of the input/output connections.
The most important parts are the logic circuits, which configure function blocks according to data in the configuration memory.
The various possible connections between functional blocks are encoded to bits known as Configuration bits. Resulting configuration stream is downloaded into configuration memory through configuration inputs.
The Fabric provides unmatched algorithmic computation power to Chameleon Chip. It consists of 84,32-bit Data path Units and 24, 16×24-bit Multipliers,Operating at 125Mhz, they provide up to 3,000 16-bit Million Multiply-Accumulates Per Second and 24,000 16-bit Million Operations Per Second.
The fabric is divided into Slices, the basic unit of reconfiguration.
The CS2112 has 4 Slices with 3 Tiles in each. Each tile can be reconfigured at runtime
Tiles contain :
Local Store Memories
Control Logic Unit
The high-performance 32bit Data path Unit (DPU): The Tile includes seven Data path Units. The DPU is a data processing module that directly supports all C and Verilog operations.
1. eCONFIGURABLE™ TECHNOLOGY:
This technology reconfigures fabric in one clock cycle.
As mentioned earlier, each Slice can be configured independently. Loading the Background Plane from external memory requires just 3 µsec per Slice; Swapping the Background Plane into the Active Plane requires just one clock cycle. with eConfigurable Technology; the four algorithms are loaded into the entire reconfigurable processing Fabric one at a time.
2. C~SIDE Development Tools :
With this software development tool , Chameleon Systems are providing the ability for the customers to do the programming themselves thus keeping the secrecy of their algorithms.
C~Side uses a combined C language and Verilog flow to map algorithms into the chip’s reconfigurable processing fabric (RPF).
It provides a interface between the Embedded Processor System and the Fabric.
eBIOS provides resource allocation, configuration management and DMA services.
A reconfigurable processor is a microprocessor with erasable hardware that can rewire itself dynamically.
This allows the chip to adapt effectively to the programming tasks demanded by the particular software they are interfacing with at any given time.
Reconfigurable processor chip usually contains several parallel processing computational units known as functional blocks.
While reconfiguring the chip, the connections inside the functional blocks and the connections in between the functional blocks are changing, that means when a particular software is loaded the present hardware design is erased and a new hardware design is generated by making a particular number of connections active while making others idle.
This will define the optimum hardware configuration for that particular software.
It takes just 20 microseconds to reconfigure the entire processing array.
Reconfigurable processors are currently available from Chameleon Systems, Billions of Operations (BOPS), and PACT (Parallel Array Computing Technology).
Among those only Chameleon is providing a design environment, which allows customers to convert their algorithms to hardware configuration by themselves.
In a conventional ASIC or FPGA, multiple algorithms are implemented as separate hardware modules. Four algorithms would divide the chip into four functional areas.
With Reconfigurable Technology, the four algorithms are loaded into the entire reconfigurable Fabric one at a time.
First, the entire Fabric is dedicated to algorithm 1; during this processing time, algorithm 2 is loaded into the background place. In a single clock cycle, the entire Fabric is swapped to algorithm 2; during this processing time, algorithm 3 is loaded into the background plane. The entire reconfigurable fabric is dedicated to just one algorithm at a time.
So finally the result is: much higher performance, lower cost and lower power consumption
Thus, a new Reconfigurable machine is established.
32-bit Risc ARC processor @125MHz
64 bit memory controller
32 bit PCI controller
reconfigurable processing fabric (RPF)
high speed system bus
programmable I/O (160 pins)
Wireless Base stations: The reconfigurable technology mainly focuses on base stations and their unpredictable combination of voice and data traffic.
Wireless Local Loop (WLL)Reconfigurable technology is widely applied in Wireless Local Loops also because of their high processing power, bandwidth and reconfigurable nature.
High-Performance DSL (Digital Subscriber Line Technology)DSL technology brings high Bandwidth to homely users.
These new chips called chameleon chips are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the outmost speed.
Its applications are in, data-intensive Internet,DSP,wireless basestations, voice compression, software-defined radio, high-performance embedded telecom and datacom applications, xDSL concentrators,fixed wireless local loop, multichannel voice compression, multiprotocol packet and cell processing protocols. Its advantages are that it can create customized communications signal processors ,it has increased performance and channel count, and it can more quickly adapt to new requirements and standards and it has lower development costs and reduce risk.
Comparison With Other Technologies
Today’s system architects have at their disposal an arsenal of highly integrated, high-performance semiconductor technologies, such as application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), digital signal processors (DSPs), and field-programmable gate arrays (FPGAs).
However, system architects continue to struggle with the requirement that communication systems deliver both performance and flexibility.
Enter the reconfigurable processor, an entirely new category of semiconductor solution that serves as a system-level platform for a broad range of applications.
can create customized communications signal processors
can more quickly adapt to new requirements and standards
lower development costs and reduce risk.
Reducing manufacturing cost.