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Transcript of LOGIC SIMULATION
SIDDHARTH SHARMA 16....06
Gate- fundamental unit of logic simulation
Possible values 0, 1, U, X.....
U- undefined memory
X- signal transitions
VHDL- allows user defined data types
if gate has "k" I/P's and "N" possible values then N^k O/p combinations need to be specified hence complexity increases.
Timing is modeled in a discrete way. All delays are integer multiple of some constant.
Different delay models are used with varying complexity
Propagation delay model
constant delay = a+nb
TYPES OF SIMULATIONS
Timing-level and macro-level Simulation
Gate-level or Logic-level Simulation
Truth table representation (multivalued)
Subroutine representation- "values using hardware instruction of computer"
Eg- "AND" instruction in C if os is C based
LOGIC SIMULATION IN VLSI CAD TOOLS
DELAY MODELING cont.
The Rise/Fall Delay model
variable rise time and fall time delays
The Inertial Delay model
Combined with both Propagation and Rise/Fall delay.
It models that the I/P pulse should have a minimum width to have effect on the O/P as needs sufficient energy to drive the gates.
Usually best for synchronous circuits if one wants to verify if patters generated by combinational circuit is correct.
We can implement constant delay models
Usually as simple as applying Longest-path algorithm.
To compute the propagation of signals the simulators have suitable data structure.
Usually graph based data structures are implemented.
Algorithm for VLSI Automation
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Electronic Design Automation For Integrated Circuits Handbook
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