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Copy of Makefile Presentation

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by

Amritpal Singh

on 28 May 2016

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Transcript of Copy of Makefile Presentation

By: Amritpal Singh
Make files
Purpose
So by this point you're probably tired of having to type:
gcc -ansi -pedantic -Wall <source_file> -o <executable>
every time you need to test a change to your code.

Problems with this approach:
Error Prone
A distraction from the debugging process
Time consuming
Inefficient on larger projects
Imagine if the process could be as simple as issuing the command "make"
How do they work?
Targets
Dependencies
Commands
all
Targets define the operations a makefile can do. They are the entry points to the makefile.

To call a target from in linux we run make <target_name> for which ever target we want make to run.

In the example to the right these are to compile each of the individual exercises, clean up emac's temporary files and remove binaries, etc.
Commands define the actual actions that should be run when that target is called.

They are always indented 1 tab from the name of the target.

They consist of one or more individual commands written just as if you were to have typed them into the terminal.
Dependencies define the targets that need to be run before the current target can be run.

For example in the case to the left the all target has each of the exercises defined as dependencies. This means that when the user calls make it will call each of the other targets defined before executing any of it's own commands (of which this example has none).

This causes all to, in the example to the left, build all of the exercises at the same time with one call to make.
all is a special target in a makefile.

It is the target called whenever we execute make without the name of a target.

In the makefile to the left calling either:

make all # because all is the target name
make

will cause the makefile to execute the same commands
Comments
Variables
Comments in makefiles are denoted using the hashtag character #

Comments are single lined, meaning that every line of comments need to be preceded with a hash tag
Variables are also similar conceptually to macros in C.

They are defined using =
CFLAGS=-ansi -pedantic -Wall

Variables are used in makefile commands by surrounding them with $(<variable_name>)
Syntax:
<target>:<dependencies>
<commands>
Any Question?
Thank you ;-)
Demo
Full transcript