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Tarandeep Singh

on 24 September 2013

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Chapters 1, 2 & 3 in a

It is concerned with the Structure and Behaviour of the Computer System , as seen by the User.
Data Representation
The Manipulation Of Binary information is done by Logic Circuits called Gates
2. And Gate - This Gate produce output 1 if both inputs are equal to 1 , otherwise the output is 0.
Karnaugh Maps - This is a method to simplify Boolean expression .

Don't Care Condition - Some Minterms are useless they don't affect anything .
We Can use it for making groups in k-maps. They are represented as X .
Includes gates , Input and Output .
An integrated circuit is a small silicon semiconductor crystal, called chip,containing the electronic components for the digital gates.
a binary code of n bits is capable of representing 2^n distinct outputs.A decoder i a combinational circuit that converts binary information from n inputs to 2^n distinct outputs.They are known as n-to-m line decoders.
A 3-to-8 line decoder
Data Representations
Binary Code
1. Or Gate - This Gate produe output 1
if input A or input B or both the inputs are equal to 1.
3. Inverter - This Gate Inverts the logic
sense of a binary signal .
5. Nand Gate - This is complement of AND Gate.
6. Exclusive OR (XOR) Gate - This Gate produces output 1 if any input is 1 but when inputs are equal to 1,then output is 0.
4. Nor Gate - This is complement of OR Gate.
Combinational Cicuits
1. Half Adder - Adds Only Two Bits .

2. Full Adder - Adds Three Bits.
SR-Flip Flop
D-Flip Flop
JK-Flip Flop
T-Flip Flop
Edge triggered flip-flops
In these types of flip flops the transitions occur at a specific level of the clock pulse.When the pulse input level exceeds this threshold level,the inputs are locked out so that the flip flop is unresponsive to further changes in inputs until the clock pulse returns to zero and another pulse occurs.Some edge-triggered flip flops cause a transition on the rising edge of the clock signal and are therefore called positive edge triggered flip flops while the ones triggered on the falling edge of the clock signal are called the negative edge triggered flip flops.
Master-Slave Flip-Flop
Sequential Circuits
Flip-flops are storage elements that can store one bit of data.These storage elements are used in sequential circuits where they are affected only at discrete instants of time by signals employed in the circuit using a clock pulse generator.
A sequential circuit is an interconnection of flip-flops and gates.There are two types of sequential circuits-synchronous and asynchronous.We are concerned with synchronous sequential circuits in which the external output is a function of both,external inputs and the present state of the flip flops.
Encoders and Multiplexers
State table
State Diagram
Excitation Table
Design Procedure
The state diagram illustrates several things:
->Various states are represented in circles,
->Transition between states is represented by lines,
->The state of the flip flops is identified by the binary numbers present inside the circle.
->Out of the two binary numbers labeled on the line,the first is the input and the second is the output.
The SR flip flop takes three inputs which are S for set,R for reset and the clock pulse.The arrowhead-shaped symbol with clock designates a dynamic input which denotes that the flip flop responds to a positive transition.
It is seldom used in practice as it produces an indeterminate next state when the value of S=1 and R=1.This problem is overcome by modifying it into the JK-flip flop.
The D(data)-flip flop is a slight modification of the SR-flip flop.SR-flip flop is converted into D-flip flop by inserting an inverter between S and R and assigning D to the single input.It has an advantage of having only one input while a disadvantage of not having a "no change" condition.However,the "no change" condition can be accomplished either by disabling the clock signal or by feeding the output back to the input.
The JK-flip flop is a refinement of the SR-flip flop such that the indeterminate condition of the SR type is defined.The inputs in J and K in a JK flip flop behave in the same way as their counterpart S and R in the SR flip flop.When the inputs J and K are both equal to 1,a clock transition switches the outputs of the flip flop to their complement state
The T flip flop is obtained from JK flip flop by connecting the J and K inputs to provide a single input.The T flip flop has only two conditions,T=0(J=0,K=0) and T=1(J=1,K=1). It is useful for constructing binary counters, frequency dividers, and general binary addition devices.
The differenciation between these chips is done on the basis of the number of gates contained by a chip...
Some systems use the master-slave flip flop.This type of circuit consists of two flip flops.The first is the master which responds to the positive level of the clock while the second is the slave which responds to the negative level of the clock.
(Exactly the opposite of a Decoder)
How it is the
Opposite ?

less than 10 gates per package
small scale integration (ssi)
medium scale integration(msi)
a = D + D + D + D
b = D + D + D + D
c = D + D + D + D
To Decimal
Forming the sum of weighted digits
10-200 gates in a single pakage
From Decimal
large scale integration(lsi)
Separate the integer and fractional parts, then divide integral part and multiply fractional part by the base
between 200 and a few thousand gates in a single package
very large scale integration(vlsi)
thousands of gates in a single packge
To Octal/Hexa
A combinational circuit that receives binary information from one of 2 input data lines and directs them to a single output line
Divide the bits into groups of four/three and write the equivalent hexa/octal codes
The number of columns for present state or next state is equal to the number of flip flops present in the circuit.The number of columns for output and input is equal to the number of output and input variables.
Present state-->state of flip flops at any given time t.
Next state-->state of flip flops one clock period later.
a b Q

(r-1)'s Complement
Formula : (r^n - 1) - N

where N is the number
r is the base
n is number of digits
(r's) Complement
Formula : r^n - N

where N is the number
r is the base
n is the number of digits
NAND gate decoder
Since a nand gate produces a and operation it becomes more economical to generate the outputs in their compliment form.
2-to-4 line decoder
->The behavior of the circuit is formulated in a state diagram.
->The number of flips flops required is determined by the number of bits within the circle of the state diagram.
->The number of inputs is specified along directed lines between circles.
->State table is obtained
->For m flip flops and n inputs,the state table consists of m columns each for present state and next state and n columns for input.
->Flip flop to be used is chosen and excitation table is obtained.
->The present states and the input columns constitute the inputs and the inputs to the flip flops as the output for the truth table of the combinational circuit.
->By map simplification we obtain a set of flip flop input equations for the combinational circuit using which the combinational circuit is derived.
->The combinational circuit together with the flip flops constitutes the sequential circuit.
it is possible to combine two or more smaller decoders with enable inputs to form a larger decoder.This is known as decoder expansion.
The excitation table is an extension of the state table consisting of a list of flip flop input excitations that will cause the required state transitions.
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