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Image Processing using FPGA

FPGA understanding and Image Processing implementation
by

SHIVANG TRIVEDI

on 31 October 2012

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Transcript of Image Processing using FPGA

Image Processing using FPGA ->FPGAs are digital ICs that contain thousands or even millions of transistors connected to perform logic functions. ->Contain configurable logic along with configurable interconnects between these logic blocks. ->Designers can configure such devices to perform functions according to the requirement. ->Field programmability is achieved through switches (Transistors controlled by memory elements or fuses) FPGA –How?? ->Switches control the following aspects Interconnection among wire segments Configuration of logic blocks ->Distributed memory elements controlling the switches and configuration of logic blocks are together called “Configuration Memory” ->FPGAs are used in Applications of FPGA Computer peripherals
Telecommunications,
Networking (switches, routers, etc)
Industrial control,
Instrumentation
Low power portable consumer electronics
Aerospace & defense ->Field Programmable Gate Array Introduction to FPGA Field : “in the field” at customer premises Programmable : “Re-Configurable” Change Logic Functions Gate Array : 2D array of gates/ logic blocks ->Programmed after manufacture rather than unchangeable ASIC. FPGA Implementation on FPGA Image Processing ->HDLs(Hardware Description Languages) are languages that are used to describe hardware for one or more following purposes :- Introduction to HDL’s Requirement Specification
Modeling
FPGA/ASIC design implementation through
Synthesis
Verification
Documentation Why HDL’s ? High Level Description Low Level
Description VHDL and Verilog are two widely used HDLs for describing FPGAs.
VHDL(VHSIC* Hardware Description Language) is originated from the language ADA and is of format of Pascal. It is widely used by Xilinx FPGAs.
Verilog is similar to C programming and is widely used by Altera FPGAs. HDLs Variants *Very High Speed Integrated Circuit VHDL vs. Verilog VHDL vs. Verilog ( contd..) VHDL Design Units Image Processing implementation ARCHITECTURE CONFIGURATION PACKAGE PACKAGE BODY ENTITY Defined Interface(I/O) Behavioral Structural Mixed (Declaration) Data types/Sub programs Functionality of Sub programs Binds a particular architecture to an entity PACKAGE GENERICS PORTS ARCHITECTURE ARCHITECTURE ARCHITECTURE ENTITY VHDL Design Units ( Connected Together) IMPLEMENTATION Elements of Entity ENTITY entity_name IS Architecture header parts Generic
Port BEGIN ( only if declarative part is used) entity declarative part Types ,subtypes, subprograms etc. for use by any
architecture for this entity END ENTITY entity_name ; Elements of Architecture ARCHITECTURE arch_name OF entity_name IS Architecture declarative parts BEGIN architecture statement part END ARCHITECTURE arch_name ; type, subtype, signal,
constant, file
subprogram,
components declartion
etc. • Process ( within process the
execution is sequential)
• Concurrent signal
assignment
• Component instantiation
• Concurrent procedure call
• Generate statement
• Concurrent assertion
statement VHDL Design Example : D Flip Flop LIBRARY ;
USE ;

ENTITY IS
PORT : IN STD_LOGIC;
: OUT STD_LOGIC

END ENTITY ;

ARCHITECTURE OF IS
BEGIN
PROCESS
IF = THEN
<=‘1’
ELSIF THEN
<= ‘0’;
ELSIF RISING_EDGE
<= ;
END IF;
END PROCESS;
<= NOT ;
END ARCHITECTURE ; IEEE IEEE.STD_LOGIC_1164.ALL DFF DFF (CLK, D, PR, CLR Q , QBAR ); BEHAVIOR TEST (CLK,PR,CLR) PR ‘1’ Q Q Q Q D BEHAVIOR QBAR (CLK) CLR=‘1’ ------------------- ----------------- ------------------- ----------------- All Words are VHDL key words Blue Library and Use Clause

DATA TYPE Concurrent
Statements
(The statements can
have any order within
architecture) IMAGE PROCESSING CONCEPTS Introduction to IP Image Processing techniques involve modifications on raw images as well as final images as per requirement. Filters Discussion 1) Rank-Order Filter
2) Convolution Filter Rank-Order Filter It comes under the category of Window Operators. it is a particularly common algorithm in image processing systems. Rank-Order Algo This filter works by analyzing a neighborhood of pixels around an origin pixel, for every valid
pixel in an image. Often, a 3x3 area, or window, of pixels is used to calculate its output. For every pixel in
an image, the window of neighboring pixels is found. Then the pixel values are sorted in ascending, or
rank, order. Next, the pixel in the output image corresponding to the origin pixel in the input image is
replaced with the value specified by the filter order. RO Pseudo code order = 5 (this can be any number from 1 -> # pixels in the window)
for loop x –> number of rows
for loop y –> number of columns
window_vector = vector consisting of current window pixels sorted_list = sort(window_vector)
output_image(x,y) = sorted_list(order) end end .
50 60 40 70 20 90 10 80 30 RO Matrix - - - - - - 50 - - Sorter Output :

10
20
30
40
50
60
70
80
90 Input Window : Output Window : median Convolution Filter Convolution is another commonly used algorithm in DSP systems. It is from a class of algorithms
called spatial filters. Spatial filters use a wide variety of masks , also known as kernels , to calculate
different results, depending on the function desired. Convolution Algo The convolution algorithm can be calculated in the following manner. For each input pixel
window, the values in that window are multiplied by the convolution mask. Next, those results are added
together and divided by the number of pixels in the window. This value is the output for the origin pixel of
the output image for that position. Convolution Matrix 50 60 40 10 20 90 70 80 30 1 1 1 1 1 1 2 1 1 - - - - - - 58 - - Input Window : Output Window : Convolution Mask : Convolution Output = (50*1 + 10*1 + 20*1 + 30*1 + 70*2 + 90*1 + 40*1 + 60*1 + 80*1)/9 = 57.7778 => 58
Thank You
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