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Microprocessor & Micro-Controller
Transcript of Microprocessor & Micro-Controller
During the 1960s, computer processors were constructed out of small and medium-scale ICs—each containing from tens to a few hundred transistors ALU (Arithmetic and Logic Unit) Cascadable 8 Bit ALU Texas Instruments SN74AS888 Definitions 1. Interrupt : Interrupts Another major feature of a microprocessor is interrupts
When many I/O devices are connected to a microprocessor based system, one or more than one of the I/O devices may request for service at any time. the microprocessor stops the execution of the current program and gives service to the I/O devices. This feature is called as interrupt.
It is an external asynchronous input or an instruction that informs the microprocessor to complete the instruction that it is currently executing and fetch a new routine in order to offer service to the I/O device. Once the I/O device is serviced, the microprocessor will continue with the execution of its normal program Microprocessor Characteristics The power of the microprocessor is determined by the following characteristics of the microprocessor Intel 4004 The Intel 4004 is generally regarded as the first commercially available microprocessor, and cost $60. The first known advertisement for the 4004 is dated November 15, 1971 and appeared in Electronic News. The project that produced the 4004 originated in 1969, when Busicom, a Japanese calculator manufacturer, asked Intel to build a chipset for high-performance desktop calculators. Intel's First Commercially
Available Micro-Processor Definitions A binary code, that indicates the operation to be performed is called as an Opcode Opcode (operation code) : The processing speed of the microprocessor depends upon the clock frequency.
The program execution speed is also determined by this parameter. The maximum clock frequency depends upon technology adapted in microprocessor fabrication. 4. Clock frequency : Microprocessor Architecture Registers
Arithmetic and logic unit
Timing and control circuitry Register Section It consists of PIPO (Parallel in Parallel out) registers as show in above figure.
This section is also called as scratch pad memory. it stores data and address of memory
The register organization affects the length of program, the execution time of program and simplification of the program. to achieve better performance the number of registers should be large.
The architecture of microprocessor depends upon the number and type of the registers used in microprocessor. It consists 8-bit registers or 16 bit registers.
The register section varies from microprocessor to microprocessor.
The registers are used to store the data and address. ALU A3 A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 F3 F2 F1 F0 Input
Operands OPCODE E.g. MOV is an Opcode which performs movement of data/valuse Operands : The data on which the operation is to be performed (as well as the result of an operation) are termed as operands. E.g. 3 + 6 = 9 in this equation 3,6,9 are the operands Instruction : The combination of the Opcode and the Operand, that can be used to instruct a system, is called as an instruction. E.g. MOV AX,1000H This instruction is used to move the data 1000H into the AX register. Instruction Set : A list of all the instructions that can be issued to a system, is called as instruction set of that system Definitions Program/Subroutine/Routine : A set of instructions written in a particular sequence, so as to implement a given task. A subroutine in assembly refers to function as in C/C++. https://www.facebook.com/ahmad.r.khan2 https://twitter.com/ahmedraza http://connectingahmad.info/fpl2.html Bus : A group of lines, pins or signals having common function is termed as bus.
The functional grouping of signals results in
1. Data bus -> to carry data
2. Address bus -> to select a memory or I/O location.
3. Control bus -> to issue and receive control signals. It is a mechanism by which an I/O device (Hardware Interrupt) or an instruction (Software Interrupt) can suspend the normal execution of the processor and get itself serviced. 2. Interrupt Service Routine (ISR) : A small program or a routine that when executed services the corresponding interrupting source is called as an ISR. 3. Vectored/ Non-Vectored interrupt : If the ISR address of an interrupt is to be taken from the interrupting source itself, it is called as a non-vectored interrupt else it is a vectored interrupt. 4. Maskable/Non-maskable interrupt : Interrupt that can be masked (disabled) or unmasked (enabled) by the programmer is called as maskable interrupt else it is a non maskable interrupt. 1. A processor is n-bit processor implies that
Its ALU is n-bit i.e. the ALU can perform n-bit operations simultaneously
Its internal data bus and register size is n-bit
Its external data bus is also n-bit (in most of the cases). 2. Processing Capability : It depends upon the number of instructions and flexibility of each instruction. 3. Word Length : It depends upon the width of internal data bus, registers, ALU etc. 5. width of the data bus : This parameter decides word length of the microcomputer. This is the width of the external data bus. 6. width of the data bus : This parameter decides the memory addressing capability of the microprocessor. The maximum size of the memory is decided by this parameter. 7. I/O addressing capability : The maximum number of the I/O ports accessed by the microprocessor depends upon the width of the I/O address provided in the I/O instruction. 8. Data types : The microprocessor handles various types of data formats like binary, BCD, ASCII, integers, real numbers, signed numbers and unsigned numbers etc. 9. Interrupt capability : Interrupts are used to handle unpredictable and randam events in the microcomputer. It is used to interrupt the microprocessor. It is also used to speed up the I/O programs. It improves the throughput of the system. Accumulator Arithmetic and
logic unit Working
register(s) Timing and clock
Circuit Stack pointer Program Counter Interrupt Circuit Register Section This architecture is divided in different groups as follows : CLK D7 Q7 D7 Q7 D6 Q6 D6 Q6 D5 Q5 D5 Q5 D4 Q4 D4 Q4 D3 Q3 D3 Q3 D2 Q2 D2 Q2 D1 Q1 D1 Q1 D0 Q0 D0 Q0 Fig. 8-bit register Outputs Inputs Arithmetic and Logical Unit This section processes data i.e it performs arithmetic and logical operations.
It performs arithmetic operations like addition, subtraction and logical operations like ANDing, ORing, Ex-ORing, etc.
The ALU is not available to the user. its word length depends upon the width of an internal data bus.
the ALU is controlled by timing and control circuit
it accepts operands from memory or register. it stores result of arithmetic and logic operations in register or memory.
It provides status of result to the flag register. Flag register shows status of result.
ALU looks after the branching decisions. Interrupt Control This block accepts different interrupt request inputs. When a valid interrupt request is present it informs control logic to take action in response to each signal. Timing and Control Unit This is a control section of microprocessor made up of synchronous sequential logic circuit.
It controls all internal and external circuits.
It operates with reference to clock signal.
This accepts information from instruction decoder and generates micro steps to perform it. in addition to this. the block accepts clock inputs, performs sequencing and synchronizing operations. the synchronization is required for communication between microprocessor and peripheral devices. To implement this it uses different status and control signals.
The basic operation of a microprocessor is regulated by this unit
It synchronizes all the data transfers.
This unit takes exact actions in response to external control signal Interfacing Buses and Significance of Bus Width A set of lines, pins, wires or signals having common function when grouped together is called a bus
The number of lines in the bus is called the bus width.
The different buses are based on their functions. In a system we come across three functions being carried out by the wires. These functions are address lines to select a memory or Input / Output location; data lines to carry data between memory, CPU and I/O devices; and control lines to carry control and status signals like enabling read or write, memory or I/O etc.
These three buses viz. address bus, data bus and control bus are found in a system, hence when these three are grouped together its is called as system bus. Applications of Microprocessor They are used in industrial control applications, calculators, instrumentation, commercial appliances, video games, toy's etc.
It is used in laboratory for training the students.
It is used as CPU of a computer. It is also used to control input, output and other devices of a computer.
They are used for word processing, database management, sorting information, scientific and engineering calculations, fuel control furnaces in a power plant etc.
They are used in smart terminals, hobby moments office automation, data acquisition systems and associated fabricated interfaces.
Controller for appliances, video games and automobiles.
They are used to measures and control the temperature of a furnace and over, the speed of an electric motor. Types of memories : Primary Memory RAM (Random Access Memory) is called so because any memory location in this IC can be accessed randomly.
There are two type of RAM, namely, SRAM (Static RAM) and DRAM (Dynamic RAM).
SRAM is made up of flip flops while the DRAM is made up of capacitors. SRAM is used in the cache memory.
Since DRAM is made using capacitors, it requires less number of components to make a one bit cell, hence also requires less space on the silicon wafer. Thus it is also comparatively cheaper. But it is slower that SRAM, because capacitors require time for charging and discharging. Also the capacitors loose charge in some time and hence need to be recharged according to the data, this is called as refreshing the DRAM. The address line selects the particular location, it enable the MOSFET that connects the capacitor to the data bus and hence if the data is to be read, simply the data line gets the data to be read; while if the data is to be written the data is to be given on the data line and will be written on the capacitor. Differences between SRAM and DRAM SRAM DRAM Cache Basics Cache operation
Principle of Locality
Cache Performance When the processor initiates a memory read bus cycle, the cache controller checks the directory to determine if it has a copy of the requested information in cache memory.
If the copy is present, the cache controller reads the information from the cache, sends it to the processors data bus, and asserts the processor's ready signal. This is called as READ HIT.
If the cache controller determines that it does not have a copy of the requested information in its cache, the information is now read from main memory (DRAM). This is known as READ MISS and causes wait state due to slow access time of DRAM.
The requested information is from the DRAM given to the processor. the information is also copied into the cache memory by cache controller and it updates its directory to track the information stored in cache memory. Address Line Transistor Storage
Capacitor Ground Bit time B Fig. DRAM Cell structure Data Output Data Input Read/Write SELECT/ Address Line S R Q Q Fig. SRAM Cell structure 1. No refreshing required. 1.Continuous refreshing required (disadvantage) 2. It is faster for accessing data. 2. It is slower in accessing data. 3. It takes more space on chip as more number
of components are required per bit. 3. It takes less space on chip as less number of
components are required per bit. 4. Hence is also costly. 4. Hence is cheaper. 5. Bit density is lesser. 5. Bit density is more. 6. The bit is stored in a flip-flop. 6. The bit is stored as a charged or discharged
capacitor. 7. SRAM is mainly used or selected for cache
memory 7. DRAM is mainly used or selected for
semiconductor main memory. Cache Operation 1. Implementation of cache memory subsystem is an attempt to achieve almost all accesses with zero wait state while accessing memory, but with an acceptable system cost.
2. The cache controller maintains a directory to keep a track of the information and it has copied into the cache memory. System Bus Host
Controller Dual- Ported DRAM
Controller System DRAM Expansion Slots Embedded Expansion
Device Embedded Expansions
Device Embedded Expansion
Device Embedded Expansion
Device System Bus System Bus Virtual Memory and Paging Virtual memory is a concept wherein the applications are made to feel that a huge main memory (fast semiconductor memory) is interfaced to the processor, whereas actually a small amount of main memory and huge external memory (typically slow ROM like magnetic disk) is interfaced.
The data is moved from the main memory in blocks (also called pages) by mechanism called as Paging.
As shown in the figure above the CPU or the PROCESSOR is connected to fast memory i.e. cache memory or SRAM which then is connected to the Main Memory or DRAM and then to the Virtual memory or the external memory.
The MMU (Memory Management Unit) connected to the processor converts the virtual address to the physical address and takes care of bringing the pages (Blocks of Data) to the main memory from external memory.
The Block Diagram of 80386DX Includes Bus Interface Unit (BIU) : 32-bit Microprocessor 80386DX Ctd... Protection Unit : Programming Model of 80386 Base architecture register Introduction to PIC18 Microcontroller Peripheral Interface Controller Principal of Locality 1. Locality of reference is the term used to explain the characteristics of programs that run in relatively small loops in consecutive memory locations
2. The locality of reference principle comprises of two components : a) Temporal Locality
b) Spatial Locality Cache Performance 1. Performance of cache subsystems depends on the frequency of cache hits, usually termed as hit rate % HIT RATE = Cache Hits Total Memory Accesses 100 % Processor MMU Cache Memory Main Memory External Memory Address Bus Address Bus Address Bus Address Bus Data Bus Data Bus Data Bus Fig:
Connection of external
or virtual memory to the
Processor This Unit includes the address drivers, transceivers for data bus and bus control signals as seen in the block diagram Prefetcher and the prefetch queue : The prefetcher fetches the instructions from the external memory and stores them in the prefetch queue to be executed further. The prefetch queue is 16-byte in size Instruction decoder and decoded instruction queue : The instruction decoder takes the instruction from the prefetch queue and after decoding it, stores them in the decoded instruction queue. The decoded instruction queue can store upto three decoded instructions. Control ROM and the sequencing logic : The control ROM provides the control signals to be issued for the corresponding instruction, which are then sequenced by the sequencing logic Execution unit : The execution unit includes a multiply unit, adder, barrel shifter and divide unit. It also includes the registers which are explained in detail in the next section i.e. programmer's model of 80386/Pentium This unit is responsible for protected mode operation of 80386 which supports multi-tasking. This will be explained in details in the subsequent sections of this chapter. Segmentation Unit : This unit is responsible for segmentation mechanism. It is also an important feature that supports multi-tasking in protected mode. This unit will be discussed in detail with the different modes of operation of 80386DX in this chapter. Paging Unit : This unit converts the linear address to physical address. a) General purpose registers
b) Instruction Pointer
c) Flag register
d) Segment registers System registers a) Memory management registers
b) Control registers Debug and test registers a) DR0 to DR7
b) TR6 to TR7 EAX AH AX AL
EBX BH BX BL
ECX CH CX CL
EDX DH DX DL
ESI SI 32 bit names 16 bit names Accumulator Base pointer Counter Data Register Stack Pointer Base Pointer Destination Index Source Index 32 bits Instruction Pointer Flags Register IP FLAGS 16 bits CS DS ES SS FS GS * * Code Segment Data Segment Extra Segment Stack Segment Fig: Base architecture registers PIC micro controllers ( Programmable Interface Controllers), are electronic circuits that can be programmed to carry out a vast range of tasks. They can be programmed to be timers or to control a production line and much more. They are found in most electronic devices such as alarm systems, computer control systems, phones, in fact almost any electronic device. PIC18 has 16-bit instruction format i.e. all the instructions are of 16-bit. There are various variants in PIC18 family that share the same instruction set and the same peripheral functional design with 8-pins to more than 80-pins chip. The peripheral functions provided by the PIC18 family are listed in the features below. 1. PIC18 is a 8-bit microcontroller that can operate at different speeds varying from DC to 40 MHz
2. The number of parallel I/O ports varies with different variants of the family
3. Pulse Width Modulation (PWM)
4. Analog to Digital Conversion with 10-bit resolution
5. Analog Comparator
6. SPI &IC serial protocols
7. SRAM & EEPROM
8. Controller Area Network (CAN)