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Ideal vs Real Op-amp

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by

Youssef Rizk

on 26 March 2015

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Transcript of Ideal vs Real Op-amp


The Ideal vs. Real Op-amp
Compare the ideal op-amp with the commercial device which you investigated in the laboratory, and explain the design strategies used to achieve the required performance.
Input Resistance
In an ideal Op-amp, the Input resistance is infinite
Real Op-amp
Experimental Measurements
The input resistance was estimated at 150 MΩ
Although impossible to produce infinite resistance, can achieve a decently large figure

Input resistance for input stage of amplified was measured at approx. 23.3KΩ
Small Signal Model
Output Impedance
Experimental Measurements
Injecting a load current into the output of the op-amp, output resistance was determined at 1.1 Ω
Output Stages of Commercial Device
Class AB Output Stage
Small Signal Model
Power/efficiency Applications
Ideal Op Amp
An ideal operational amplifier has infinite open loop gain at all frequencies thus GB should be infinite => does not make sense for it to exist.
Real Op Amp?
Ideal Op-amp
Output impedance is zero
Zero output impedance is impossible to produce, but, low values can be obtained
Open-loop output impedance is quoted at 30 Ω
Macro-model Op-amps
MOSFET Vs. BJT Application
Class B Output Stage
Output Impedance is simply the emitter resistance, excluding the source resistance
Emitter Follower configurations have high current gain
Bandwidth is defined as the frequency at which the gain falls to 0.7 of its DC value
Conclusion
Bandwidth
Crossover Distortion
Differential Gain
Ideal Op-amps have infinite differential gain
Real Op-amps tend to have finite values, typically around the order of 10^5
Through negative feedback, the actual gain of an op-amp circuit can be made independent of the open loop gain
High differential gain is achieved through multistage amplifiers
First Stage:
Small Signal Analysis Shows:
Second Stage: Common Emitter Circuit
Given input: 8 mV p-p
Output: 10 V p-p
Gain = 1250
Initial Gain Stage
High Gain Stage
Third Stage: Output
Low gain Stage
Ideally, op-amps should strictly amplify the differential input voltage.
In reality, disturbance signals present at both inputs are also amplified, known as
Common-Mode Gain

Small Signal Common-mode gain

Common-Mode Rejection Ration (CMRR)
Ratio of Differential to Common-mode gain
With
and
To reach more Ideal Behavior, Emitter Resistance has to be increased
Limit: Gain Bandwidth Product
Notice: Break point
The point at which the frequency starts to roll off is known as the break point [typically the -3dB point is known as the break point].
The half power point of an electronic amplifier stage is that frequency at which the output power has dropped to half of its mid-band value. That is a level of -3 dB.
So what is -3db? Why at -3db?
Note that it is output power that dropped by half, voltage drops by 1/[sqrt(2)]!
However
in actual op amps,
Also
adding feedback -> sacrificing gain for bandwidth
Ideal Real
Infinite open loop gain Finite open loop gain >10^5
Infinite input impedance Finite input impedance >150MΩ
thus zero input current
Zero input offset voltage Exists due to imperfections in the differential
amplifier that constitutes the input stage
Infinite output voltage range Finite output voltage range due to saturation, limited
to the minimum and maximum value close to the
power supply voltages
Infinite bandwidth and infinite Finite bandwidth limited by GBP, slew rate limited by
slew rate input stage saturation
Zero output impedance Finite output impedance of around 30Ω
Zero CM Gain Finite CM Gain due to imperfections in the differential
input stage, leading to the amplification of these
common voltages
Output Voltage Range
Ideally, infinite range.
The output should be Gain x Input
However
in actual op amps,
Output voltage is limited to a minimum and maximum value close to the power supply voltages
Saturation occurs
Experiments:
Test 1 - Simple Current Mirror
Test 2 - Improved Current Mirror
Single stage C-E Amplifier
Test 3 - Voltage Gain and Input Resistance
Test 4 - C-E Stage with Active Load
Test 5 - Differential Voltage Gain and Input Resistance
Test 6 - Common-Mode Voltage Gain and CMRR
Test 7 - Cross Over Distortion
Test 8 - Current Limit and Short Circuit Output Protection
Test 9 - Frequency Compensation
Test 10 - Bandwidth and Tests
The Op Amp Lab Oral Presentation
26 March 2015
Based on Op-amp Applications and Design
Trade-off
Thank you!
GB = Bandwidth x Open Loop Gain
Adding a capacitor
Avoid the situation where the output for negative feedback lags behind the input by 360 degrees resulting in positive feedback
Ensures the op amp remains stable and does not produce unwanted high frequency spurious oscillations
Input Offset Voltage
The input offset voltage is defined as the voltage that must be applied between the two input terminals of the op amp to obtain zero volts at the output.
0 V
0 V
?
Output should be 0 volts
However
in actual op amps,
Ideal Op Amp
Due to manufacturing process, the differential input transistors of real op-amps may not be exactly matched => this causes the output to be zero at a non-zero value of differential input
While for Op Amp Design, the transistors SSM2210 has a V(os) of about 10μV while our SSM2220 has a V(os) of about 40μV, both max at 200μV
Our SSM2210 and SSM2220 has a GB of 200MHz and 190 MHz respectively
For early Spring Term Op Amp Application, we found that the experimental value of V(os) of the op amp given to us in the test box was 3 mV
Give higher speeds for same dimension and price due to smaller capacitance => Miller effect
Better gain characteristics => fewer gain stages
Better fidelity as gain does not depend on bias voltage (vs MOSFET)
Easy to scale => to half current just half gate length
High input impedance => almost infinite at low frequencies
Consume less power as output controlled by input voltage, not current (vs BJT)
Easier to make identical FET (vs BJT)
So BJT or FET?
BJT
FET
So PNP or NPN?
If you want something to be OFF and you turn it ON => NPN
If you want something to be ON and you turn it OFF => PNP
Well-made commercial devices could employ BJT's and MOSFET's in various stages
Full transcript