IC LAYOUT PRESENTATION

Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shape which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit. IC Station configurations are built from a family of IC design tools which covers all the needs for advanced IC design. From floor planning, to layout creation and assembly, and on to verification, Mentor Graphics' IC Station supports all the capabilities a designer needs for every step of his design process.

Design Rules Checking (DRC) used as verification tools that checks the layout geometry to make it obeys set of design rules such as minimum widths and spacing, extensions and overlaps. In other word, DRC is done to verify that all rules are met. It highlights places that rules fail and state the reasons

Layout Versus Schematic (LVS) compares the layout and schematic cell views. LVS is used to ensure that your layout is identical to your schematic. LVS works by generating a new netlist for the layout. It then compares this netlist with schematic’s netlist. If any discrepancies are found, LVS will display them.

AFTER SIMPLIFICATION

SCHEMATIC DIAGRAM

TEST BENCH

WAVEFORM

SCHEMATIC DIAGRAM

TEST BENCH

WAVEFORM

EULER PATH

STICK DIAGRAM

LAYOUT BEFORE CHECKER

BEFORE CHECKER

FIRST ERROR

SECOND ERROR

THIRD ERROR

AFTER CHECKER

BEFORE

FIRST ERROR

AFTER LVS CHECKER

Intergrated Circuit (IC) Layout design is one of the most important process before we proceed to wafer

fabrication process. As we know, the IC layout engineer design the mask which will be used during wafer fabrication process to print all the circuit onto the wafer. So, a single mistake in IC Layout design will lead to many unnecessary error, or even worst money loss. We are glad because we get to learn most of the common process IC Layout engineer do due to our mini project.

• Boolean equation and asked to simplify it.
• Design the schematic diagram for the particular boolean equation.
• Analyses the waveform.
• Proceed to design the Layout Design.
• The generated layout must pass a series of physical verification.
• Design rules checking (DRC) .
• Layout versus schematic (LVS).

After both of the process check are done, thus our mini project has come to an end. We are glad to given

chance to learn what a IC layout design engineer will do and also what they should do. Both of us agree that IC layout design engineer are not an easy job as what we mentioned above.A single error in design will cause a lot of trouble to every process after it. It is also because of that which make IC layout design engineer so important. We would like to express our thank to all the IC layout design engineer and also not to forget to out beloved lecture, Puan.Faradilla binti Aziz for helping us alot in this mini project. We are also glad to given chance to learn the IC layout design process from the scratch.

• From the mini project, we learnt how to design a circuit base on the equation given thus create a test bench diagram and finally view and analyse the output waveform.

• Next, we know how to design a stick diagram which is a simple way of floor-planning a circuit in preparation for layout. Furthermore, we know how to RELATE AND ILLUSTRATE the masks and layout drawing as circuit representations. We can EXPLAIN AND APPLY sticks diagram in Layout design. We also know how to DEFINE AND APPLY the well, body contacts, contacts and vias in mask layout. Next, EXPLAIN AND ILLUSTRTATE the multilayer interconnections.

• For Layout Verification, we learnt how to IDENTIFY AND APPLY the Design Rules Check (DRC), Layout Versus Schematic (LVS) during Layout verification.