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GF Lead & Mentor (IPTST & Memory IP)
Uttam Saha
GF Lead & Mentor (Analog IP Development)
Shivraj Gurpadappa Dharne
The Team
Lead, IPTST Team
Sr. Engineer, Ulkasemi Inc.
Lead, IP Development Team
Sr. Engineer, Ulkasemi Inc.
Asst. Engineer, Ulkasemi Inc.
Asst. Engineer, Ulkasemi Inc.
Asst. Engineer, Ulkasemi Inc.
IP development Overview
IPTST Overview
Accomplishments
Jan, 2020 - June, 2020
1. 1.6 GHz Phase Locked Loop in 28nm (28SLPe)
2. Ramp Generator (Integrator) in 28nm (28SLPe)
3. Current Mode Logic Buffer in 12nm (12LP)
4. Current Mode Logic to CMOS logic Converter in 12nm (12LP)
5. CMOS logic to Current Mode Logic Converter in 12nm (12LP)
Memory IPTST
8x32 Array
8x64 Array
8x128 Array
- Three exisitng memory bitcell array in 28SLPe.
- Expandable to any other technology as well.
In 28SLPe
We call it
The GUI
IPXtreme 1.0
IPXtreme 1.0, the IPTST GUI, has the following features:
Next Steps