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IMPLEMENTATION
8-BIT ADDER AND SUBTRACTOR
FIELD PROGRAMMING GATE ARRAY(FPGA)
1.A field-programmable gate array (FPGA) is an integrated circuit (IC) that can be programmed in the field after manufacture.
2. Ultimately, FPGAs might allow computer users to tailor microprocessors to meet their own individual needs.
A 8-BIT ADDER AND SUBTRACTOR
1.In 8 bit binary parallel adder-subtractor there are 8 full adder connected in a parallel way.
2. The addition and subtraction can be combined into one common circuit by including an exclusive-OR gate with each full adder.
OBJECTIVES-
1. Theoretical aspect of project
2.Learn about hardware description language i.e. verilog
3.Develop the design with various modeling styles.
4.FPGA implementation of the design
BLOCK DIAGRAM
TRUTH TABLE
1.Verilog is a HARDWARE DESCRIPTION LANGUAGE(HDL).
2. It is a language used for describing a digital system like a network switch or a microprocessor or a memory or a flip−flop.
3. Through Xilinx we have implemented our project.
1. BEHAVIORAL LEVEL:
This level describes a system by concurrent algorithms (Behavioral). Every algorithm is sequential, which means it consists of a set of instructions that are executed one by one.
2. REGISTER-TRANSFER LEVEL:
Designs using the Register−Transfer Level specify the
characteristics of a circuit using operations and the transfer of
data between the registers.
3. GATE LEVEL:
A gate level description consists of a network of gates and registers instanced from a technology library, which
contains technology-specific delay information
for each gate.
OUR PROJECT
TO MAKE THE 8-BIT ADDER WE HAVE MADE A FULL ADDER MODULE AND CALLED IT EIGHT TIMES FROM THE MAIN MODULE FOR EACH BIT. FOR SUBTRACTION PURPOSE WE HAVE IMPLEMENTED X-OR GATES WHICH GIVE THE 2'S COMPLEMENT OF THE NUMBER TO BE SUBTRACTED AND THEN BOTH THE NUMBERS ARE PASSED IN THE FULL ADDER WHICH ADDS THEM AND FINALLY THE ORIGINAL NUMBERS ARE SUBTRACTED.
OUTPUTS
MODY UNIVERSITY OF SCIENCE AND TECHNOLOGY
(COLLEGE OF ENGINEERING AND TECHNOLOGY)
B.TECH(IInd YEAR SPRING SEMESTER)
COMPUTER ORGANIZATION AND ARCHITECTURE (CS 14.208)
PRESENTED BY: UNDER GUIDANCE OF:
AASHI JAIN(150158) Mr. GAURAV DHIMAN
AASTHA SHARMA(150159)
AASTHA GUPTA(150160)
ADHISHI POKHARNA(150161)
ADITI SINGH(150162)
REFERENCES
1. M.Morris Mano ,Computer System Architecture,Pearson Education .
2. Carl Hamacher,Zvonko Vranesic and SafwatZaky, Computer Organization , Tata McGraw Hill
3. www.tutorialspoint.com
1. The digital circuit that generates the arithmetic sum of two binary numbers of any length is called binary adder.
2. A Binary Subtractor is a decision making circuit that subtracts two binary numbers from each other, for example, X – Y to find the resulting difference between the two numbers.