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Function:
Function in FPGA:
Function:
Function in FPGA:
Function:
Function in FPGA:
Function:
Function in FPGA:
Politechnic University of Aguascalientes
library ieee;
use ieee.std_logic_1164.all;
entity final is
port (CLK50: in std_logic;
ledbar: out std_logic_vector(7 downto 0);
up, down: in std_logic;
ledR, ledV, clock: out std_logic;
uni,dec: out std_logic_vector(6 downto 0));
end final;
architecture system of final is
signal output: integer range 0 to 7;
signal clkcount: integer range 0 to 25000000;
signal state: std_logic;
signal count: integer range 0 to 25000000;
signal u,d: integer range 0 to 15;
signal k: integer range 0 to 44;
signal b,x,y,z,q: std_logic;
begin
process (CLK50)
begin
if (rising_edge(CLK50)) then
if(clkcount=5000000)then
clkcount <= 0;
output <= output+1;
else
clkcount <= clkcount+1;
end if;
end if;
if (output=8)then
output <= 0;
else
if k=0 then
ledbar <= "00000000";
output <= 0;
ledR <= '1';
ledV <= '0';
else
case output is
when 0 => ledbar <= "10000000";
when 1 => ledbar <= "11000000";
when 2 => ledbar <= "11100000";
when 3 => ledbar <= "11110000";
when 4 => ledbar <= "11111000";
when 5 => ledbar <= "11111100";
when 6 => ledbar <= "11111110";
when 7 => ledbar <= "11111111";
end case;
ledV <= '1';
ledR <= '0';
end if;
end if;
end process;
process (CLK50)
begin
if (rising_edge(CLK50)) then
if(count=250000)then
state <= not state;
count <= 0;
else
count <= (count+1);
end if;
end if;
end process;
clock <= state;
process(state,u,d)
begin
if (rising_edge(state)) then
if (up='0') then
x<='1';
if (x='1' and y='1') then
if(k=44) then
u<=4; d<=4;
else
u <= u + 1; k<=(k+1); x<='0';y<='0';
if u = 9 then
u <= 0;
d <= d + 1;
if d = 9 then
d <= 0;
end if;
end if;
end if;
end if;
else y<='1';
if (down ='1') then
z<='1'; else q<='1';
if (z='1' and q='1') then
u <= u - 1;z<='0';q<='0'; k<=k-1;
if u = 0 then
d <= d - 1;
u <= 9;
if d = 0 then
d <= 0; u<=0; k<=0;
end if;
end if;
end if;
end if;
end if;
end if;
case u is
when 0 => uni <= "0000001";
when 1 => uni <= "1001111";
when 2 => uni <= "0010010";
when 3 => uni <= "0000110";
when 4 => uni <= "1001100";
when 5 => uni <= "0100100";
when 6 => uni <= "0100000";
when 7 => uni <= "0001111";
when 8 => uni <= "0000000";
when 9 => uni <= "0000100";
when others => uni <= "0001000";
end case;
case d is
when 0 => dec <= "0000001";
when 1 => dec <= "1001111";
when 2 => dec <= "0010010";
when 3 => dec <= "0000110";
when 4 => dec <= "1001100";
when 5 => dec <= "0100100";
when 6 => dec <= "0100000";
when 7 => dec <= "0001111";
when 8 => dec <= "0000000";
when 9 => dec <= "0000100";
when others => dec <= "0001000";
end case;
end process;
end system;
Jorge Barrera Landaverde
(UP090254)
(UP100739)
Salvador Simental Covarubias
Electronic system that allow control in an automatic way the in and out in a parking