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CH5 COMBINATIONAL MSI
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CH5 MSI ELEMENTS/ CIRCUITS
MSI (Medium Scale Integrated) ELEMENTS
SSI (Single Scale Integrated) Elements has integrated 0-10 GATE elements
MSI (Medium Scale Integrated) Elements has integrated 10-100 GATE elements
LSI (Large Scale Integrated) Elements has integrated 100-1000 GATE elements
VLSI(Very Large Scale Integrated) Elements has integrated more than 1000 GATE elements.
MSI
ELEMENTS
Medium and Large scale integrated elements
- might have additional control inputs
- apart from the independent data input variables.
- These inputs improves the functionality of the elements.
Most common MSI Elements:
- Decoder/Encoder
- Multiplexer (Mux)
- Parallel Adder
- Look ahead carry
- Adder/ Subtractor
- BCD (Binary Coded Decimal) adder
- Multiplier
- Comparator
DECODER ELEMENT: 3X8 DECODER
3X8 size decoder:
- x,y,z: inputs,
- m0-m7 8 outputs,
- active output is (1),
- no control input
- any binary input code, makes one of the output active.
- In other words by observing the output (decoding)
- one could say the input code.
- Boolean explanation is that
- all the minterms of a three-variable function
- are determined.
DECODER ELEMENT
2X4 DECODER WITH ENABLE
2X4 DECODER WITH ENABLE
function table
Function table vs Truth table:
- If E(enable) input =1
- then all the outputs are equal to (1)
- where inputs shown as 1xx
- represents 4 rows 100, 101, 110,1,11.
- Truth table has 8 rows
- but function table has only 5 rows
- x,y,z: inputs,
- m0-3 4 outputs,
- active output is (0).
- one control input (E).
- E=0 makes the output (1)
- independent from the other inputs (x, y)
- means decoder does work,
- in other words decoder inactive (not enable) .
- When E=0
- then decoder works properly.
What is the Boolean explanation of the outputs?
SIZE INCREASE BY ENABLE
- How to increase decoders size
- by using lower size decoders:
- use enable control input.
How you can get a 4X16 size
by using 2X4 size decoders?
ENCODER
ENCODER
Classical approach:
- 8 input variable, 2^8=256 different inputs which has 244 don't care values. Give up!
alternative:
- X = m4+m5+m6+m7
- Y = m2+m3+m6+m7
- Z = m1+m3+m5+m7
- m0=1 would not be problem.
Problem
- When more than one input variable is (1) at the same time,
- wrong output may be observed such as:
- 3 and 6 inputs are (1) causes 7 output! Problem
- solution priority encoder see MANO
Consider PC keyboard,
how you could apply
different characters
to a digital system?
FUNCTION SYNTHESIS EXAMPLE: MSI FULL ADDER
Any n-variable function can be realized
by an (nX2^n) size- decoder
with an additional OR gate
of which FAN-IN
is equal to number of true minterms.
FUNCTION SYNTHESIS
If there are m number of
n- variable functions to be realized
then one nX2^n size decoder
with additional m number of OR gates would be adequate.
Pro and con:
- MSI design no need any
- "SSI design technique"
- QMC or
- Karnaugh map
- to apply.
What could be con?
Does number of functions to be designed, affect number of decoders to be used?
2X1 MULTIPLEXER (MUX)
2X1 MULTIPLEXER
- 2 Input (I0, I1)
- 1 Control input (S)
- 1 Output (Y)
MULTIPLEXER
Definition
S=0 z=I0
S=1 z=I1
Find truth table?
find function table
4X1 MULTIPLEXER
Function table
4X1 MULTIPLEXER
- 4 Input (I0, I1)
- 2 Control input (S)
- 1 Output (Y)
4X1 MUX
General
- 2^nX1 MUX:
- 2^n INPUTS
- n control inputs
- 1 output
- Interpretation:
- Leading the data coming from
- four different sources
- (I0,I1, I2, I3)
- to a destination
- (Y, output)
- under the control inputs
- s0 and s1.
FUNCTION REALIZATION BY MUXES
FUNCTION REALIZATION
Any variable functions can be realized
by muxes
3-VARIABLE FUNCTIONS REALIZATION
3-VARIABLE FUNCTION REALIZATION
8X1 mux no additional gate
4X1 mux one additional NOT gate
4-VARIABLE FUNCTIONS
GENERALIZE MUX USAGE FOR FUNCTION REALIZATIONS
- Assume that
- there is a n-variable function
- to be designed,
- Which mux size requires
- what additional gates?
4-VARIABLE FUNCTION REALIZATION
Compare the function realizations being examined up to now:
- Which one
- is preferable?
- When?
- Why?
SWITCHING CIRCUIT
DECODER
AS DEMUX
If a decoder's
- enable control input
- and data inputs
- roles are interchanged
then decoder becomes demux
- which does the opposite of mux.
- Such a property
- can be used in "switching"
SWITCHING CIRCUIT
SINGLE LINE SWITCHING
SINGLE LINE SWITCHING
"SWITCHING" PROCESS WITHIN COMMUNICATION:
- one side "sources": X, Y, Z, W mux inputs
- the other side "destinations":A,B,C,D,E,F,G,H decoder outputs
- Any pair one from source side and other from the destination side could communicate
- by the data select control inputs of mux and
- decoder inputs as data select (de mux).
- Lİne between Mux output and decoder "enable" input
- is communication media (transmission line) called "trunk" .
Example:
- (Y and E) can communicate through trunk
- if mux data select (01)
- while decoder data select is (101).
- The same trunk could also be shared
- by other pairs
- in an another time interval.
If we did not have such a system for communication
- what would be solution? OR
- What is the benefit of such a switching system?
What should be data select inputs in order transfer X data to H destination?
Switching here can be interpreted as physical connection between two terminals.
It can also be interpreted as time sharing of a physical media (trunk).
4-LINE SWITCHING
4-LINE (4-bit) PARALLEL SWITCHING
- A: 4-bit data source1
- B: 4-bit data source 2
- Y: 4-bit parallel data lines
- (BUS, transmission lines, comm media)
- E control input: enables whole system
- S control input: select the source from A and B
- What should be mux /decoder sizes in order to transfer 8-bit data
- from four different sources to
- four different destinations?
Parallel switching will increase communication capacity, why?
PARALLEL ADDER
4 full adder circuit integration makes a MSI adder.
Compare BCD- excess3 designs:
MSI
SSI
MSI 4-BIT ADDER
PARALLEL ADDER
capacity of such an adder is very limited.
- two numbers
- 4-bit each
How this capacity could be increased when required?
ADDER / SUBTRACTOR
CARRY LOOK AHEAD MSI ADDER
MSI 4-bit adder delay time is
- 4x(full adder delay time).
- In general if n-bit- numbers to be added
- the delay time is equal to
- n times (full adder delay).
Question: could this delay time reduced? How?
Answer:
Look ahead carry MSI ADDER
LOOK AHEAD CARRY MSI ADDER
Comparison:
4-bit MSI adder: 12 gate delays
4-bit Look ahead carry MSI adder?
BCD (BINARY CODED DECIMAL) ADDER
4 bit MSI binary adder requires binary conversions of decimal numbers.
- This is not easy operation done as logic circuit.
- Solution could be decimal numbers (BCD) representation.
- Each digit of the decimal number is separately represented
- by four-bit-binary. Example: 752--> 0111 0101 0010
Observations:
- BCD numbers could be highest decimal 9, why?
- The highest sum number could be 19, why
BCD ADDER
BCD adder for each digit could be designed
- by two 4-bit-binary-adders
- and an additional combinational circuit as shown (see right )
If the first 4-bit adder's sum output is more than 10,
- then 10 should be subtracted (which is 0110 in 2's complement)
- and a carry (1) should be added to the higher digit.
Consider the inputs of the additional logic as
- K (first 4-bit-binary-adder carry) ,
- Z4, Z3, Z2, Z1 (Sum of 4-bit-binary-adder)
Consider the output of the additional logic as
- C detects sum(Z4, Z3, Z2, Z1) is 10 or more.
- C also shows carry out
Second 4-bit-binary-adder output (S4,S3,S2,S1) is BCD sum.
MULTIPLIER
MULTIPLIER
COMPARATOR
What happens if use classical design?
- How many inputs how many outputs?
- Is it practical?
An algorithmic approach has been preferred.
Would it be enough to have two outputs? hint:coding
Why three outputs?
COMPARATOR
Why it has been avoided to have a comparator circuit for binary subtraction?
What has been considered for subtraction?