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- Viterbi Decoder
- axi DMA
- Filter RX
SDK
BIN Deployment
SDK
IP Integration
Vivado
IP Integration
Vivado
Export SDK
BSP
HLS
IP Deployment
Vivado
Synthesis
Vivado
BitSteam
Source Code
C / C++ Code
Vivado
Place & Route
HLS
Cosimulation
HLS
gcc Compiler
Minir Code Modification
HLS
Synthesis and
HW Tunning
HLS
Code Verification
TestBench
3 HW accelerators have been designed:
-Demodulator, Viterbi Decoder and Filter48 Taps;
-The IP interface: axi-stream and axi lite
-The Maximum Data trasfer rate is 9.6GB/sec.
-The DMA IP is exploited
- Fixed floating point datatype is used.
- 100% of C Code Reused
- 0 % VHDL
- Cosimulation is VERY FAST!!!
How design an HW Accelerator
Using predefined options on BSP and gcc is possible to measure the timecall and total number of call of each functions . Gmon.out
3 System
Optimization
1st Tx integration and verification
2nd RX integration and verification
Minor software modifications i.e.pointers management
Tips:
There are 100 of ready to use ARM libraries, here after the ,most common one.
The RX code has been optimized exploting:
Tips: The sotware modifications do not require to regenerate the bitstream neither the BSP. thus are simple and fast to check.
Performances: [Bitrate 3200 300 byte]
Required Processing time
2400 416us
3400 277 us
6400 156 us
8000 125us
9600 100 us
More than 95% of processing is allocated on SW.
Current Zynq design can demodulated up to 6400 bps
additional modifications are needed to accommodate 8000 and 9600 bps modulation.
FPGA occupancy < 15%
- The RX process is under the governance of a SM
- There is a Massive use of pointers
- There is a Massive use Matrix operations inv, multiplication etc
-Changing the data type from double to float or fixpoint, should
improve drastically the performance. However this option is not
efficient due to the extensive modifications to be made on the source code.
- The approach taken is to optimize the SW locally changing "ground" routing i.e. lsl lsr pow2 InvMatrix etc; moreover integrating HW accelerators that operate in pipeline with Processor, reducing the
processor workload.
- HW Developer kit ZedBoard Zynq 7020
- Design Tools: Vivado, SDK and HLS
- Thirdpart libraries: RTOS and LWIP
Traditional Flow
ZYNQ & HLS
Development
Platform
ALL IN ONE
Deployment
Platform
Design
Platform
Verify the effectiveness of Xilinx tools
- High Level Synthesis (HLS)
- Zynq HW platform
C. S.: Porting of Mil-std 188 HDR 110B-C
ZYNQ & HLS
1-2 Gops
HDR 110B
10-1000+Gops
Vivado High-Level Synthesis accelerates IP creation by enabling C, C++ and System C specifications to be directly targeted into Xilinx All Programmable devices without the need to manually create RTL.