SAP1 (Simple-As-Possible) Computer

Presented By:

Bayani, Louie Dave

Lopez, Gio Mark

Romanes, Raniline

Sarmiento Allan Paul

Submitted To:

Engr. Alex Caparas

SAP1 (Simple-As-Possible) Computer

ALU

Memory

• MAR

Control Unit

• Accumulator
• B register
• Adder-subtracter

I/O unit

• PC
• Controller-Sequencer
• IR

• Input programming switches
• Output port
• Binary display

Adder-Subtracter

Output Register

Binary display

Controller-Sequencer

• 2’s complement adder-subtracter
• When SU is low, S = A + B
• When SU is high, S = A + B’
• When EU is high, the content appears on the W bus

• Often called the output port
• When EA is high & L’O is low , the next (+) clock edge loads the accumulator word into the output registe

16 x 8

• Row of 8 LEDs
• Each LED connects to 1 flip-flop (FF) of the output port

• The 12 bits coming out of the CS form a word that controls the rest of the computer.
• The 12 wires carrying the control word are called CONTROL BUS.
• The CS sends out control words on during each T STATE.
• These words are like directions telling the rest of the computer what to do.

Architecture

B Register

Instruction Register

RAM

INPUT AND

MEMORY ADDRESS REGISTER (MAR)

• There are 16 memory locations and each location contains an 8 bit of data.

• Another 8-bit wide buffer register
• Used in arithmetic operations
• When L’Bis low & (+) clock edge, the word on the W bus will be loaded

• Loads the content of the addressed memory location through the W bus
• Upper nibble goes directly to the Controller-Sequencer
• Lower nibble is read onto the W bus when needed

• The MAR stores 4 bit address of data and instruction which are placed in memory.
• When SAP-1 is running mode, the 4 bit address is generated by the PC which is then stored into the MAR through W bus.
• a bit later, the MAR applies this 4 bit address to the RAM, where Data or instruction is read from RAM.

16 x 8

• Program counte
• Input & MAR
• Instruction Register
• Controller Sequencer
• Control word format
• Accumulator
• Adder-Subtracter
• B Register
• Output Register
• Binary Display

Accumulator

Control word format

Program counter

• Buffer register
• 8-bit wide
• When EAis high, the content appears on the W bus

• Generated by 4-bit Program Counter, that counts from 0000 to 1111 (total of 16 memory locations).

• This word determines how the registers will react to the next positive CLK edge
• Ex. EP = high, L’M = low – mean that the contents of PC are latched into the MAR on the next (+) clock edge
• Ex. CE’= low, L’A = low – mean that the addressed RAM word will be transferred to the accumulator on the next (+) clock edge

SUB

• Ex SUB 2H
• Subtracts the content of memory location 2H from the accumulator content, save the result to the accumulator
• Content of R3 is loaded to B

OUT

ADD

• Transfer the accumulator content to the output port

HLT

• Tells the computer to stop processing data

• Ex ADD 3H
• Adds the content of memory location 3H to the accumulator content, save the result to the accumulator
• Content of R3 is loaded to B

Memory-reference instructions

• LDA, ADD, SUB

Not Memory-reference instructions

LDA

• OUT, HLT

• Load the accumulator
• Ex LDA 5H (R5 = 1010 1111)
• A = 1010 1111

Mnemonics

• abbreviated instructions

STATES

Instruction Set

Fetch Cycle

EXECUTION CYCLE

SAP1

• upward compatible with the 8080/8085 instruction set

LDA 9H

ADD AH

SUB BH

OUT

HLT

• The next three states (T4, T5, & T6) are the EXECUTION CYCLE of SAP 1.
• The register transfers during the execution cycle depend on the particular instruction being executed.

• The T1 state is called the ADDRESS STATE because the address in the PC is transferred to the MAR during this state.
• The T2 state is called the INCREMENT STATE because the PC is incremented.
• The T3 state is called the MEMORY STATE because the addressed RAM instruction is transferred from the memory to the IR.
• The address, increment & memory states are called the FETCH CYCLE of SAP 1.

• The CONTROL UNIT is the key to a computer's automatic operation. The CU generates the control words that fetch and execute each instruction.
• While each instruction is fetched and executed, the computer passes through different TIMING STATES (T states) time intervals during which register contents change.
• Ring counter has an output of T = T6 T5 T4 T3 T2 T1
• Each ring word represents one T STATE.
• The ring counter produces 6 T states. Each instruction is FETCHED & EXECUTED during these 6 T states.