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PROCESSOR MODES

1. INTERRUPTS

MASK INTERRUPTS: RECEIVED ON THE PROCESSOR'S INTR PIN. THE PROCESSOR DOES NOT RECOGNIZED A MASKABLE INTERRUPT UNLESS THE INTERRUPT ENABLE FLAG IS SET.

NON MASK INTERRUPTS: RECEIVED ON THE PROCESSOR'S NMI PIN. RECOGNITION OF SUCH INTERRUPTS CANNOT BE PREVENTED.

2. EXCEPTIONS

PROCESSOR-DETECTED EXCEPTIONS: RESULTS WHEN THE PROCESSOR ENCOUNTERS AN ERROR WHILE ATTEMPTING TO EXECUTE AN INSTRUCTION.

PROGRAMMED EXCEMPTIONS: THESE ARE INSTRUCTIONS THAT GENERATE AN EXCEPTION.

IT IS QUITE COMMON FOR A PROCESSOR TO SUPPORT ONLY A SMALL NUMBER OF PROCESSOR MODES.

THE EXCEPTION MODES HAVE FULL ACCESS TO SYSTEM RESOURCES AND CAN CHANGE MODES FREELY. THE EXCEPTION MODES ARE AS FOLLOWS:

*SUPERVISOR MODE *ABORT MODE

*UNDEFINED MODE *FAST INTERRUPT MODE

*INTERRUPT MODE

REGISTER ORGANIZATION

entered in responce to memory faults.

usually what the OS runs in. it is entered when the processor encounters a softer interrupt instruction. software interrupts are a standard way to invoke operating system services on ARM.

THE ARM PROCESSOR

entered when the processor attempts to execute an instruction that is supported neither by the main integer core nor by one of the coprocessors.

entered whenever the processor receives an interrupt signal from the designated fast interrupt source. a fast interrupt cannot be interrupted, but a fast interrupt may interrupt a normal interrupt.

entered whenever the processor receives an interrupt signal from any other interrupt source. an interrupt may only be interrupted by a fast interrupt.

MMX REGISTERS

IS A MODERATE ARRAY OF UNIFORM REGISTERS, MORE THAN ARE FOUUND ON SOME CISC SYSTEMS BUT FEWER THAN ARE FOUNDON MANY RISC SYSYTEMS

virtual-8086 mode extension

protected-mode virtual interrupts

time stamp disable

debugging extensions

page size extensions

physical address extension

machine check enable

page global enable

performance counter enable

REGISTERS ARE ARRANGE IN PARTIALLY OVERLAPPING BANKS, WITH THE CURRENT PROCESSOR MODE DETERMINING WHICH BANK IS AVAILABLE. AT ANY TIME, SIXTEEN NUMBERED- REGISTERS AND ONE OR TWO PROGRAM STATUS ARE VISIBLE, FOR A TOTAL OF 17 OR 18 SOFTWARE-VISIBLE REGISTERS.

INTERRUPT PROCESSING

PROCESSOR ORGANIZATION

THE MMX INSTRUCTIONS MAKE USE OF 3-BIT REGISTER ADDRESS FIELDS, SO THAT EIGHT MMX REGISTERS ARE SUPPORTED. IN FACT, THE PROCESSOR DOES NOT INCLUDE SPECIFIC MMX REGISTERS.SOME KEY CHARACTERISTICS OF THE MMX USE OF THESE REGISTERS ARE AS FOLLOWS:

THE AR PROCESSOR ORGANIZATION VARIES SUBSTANTIALLY FROM ONE IMPLEMENTATION TO THE NEXT, PARTICULARLY WHEN BASED ON DIFFERENT VERSIONS OF THE ARM ARCHITECTURE. HOWEVER, IT IS USEFUL FOR THE DICUSSION IN THIS SECTION TO PRESENT A SIMPLIFIED, GENERIC ARM ORGANIZATION.

WITHIN A PROCESSOR IS A FACILITY PROVIDED TO SUPPORT THE OPERATION SYSTEM. IT ALLOWS AN APPLICATION PROGRAM TO E SUSPENDED, IN ORDER THAT A VARIETY OF INTERRUPT CONDITIONS CAN BE SERVICED AND LATER RESUMED.

CONTROL REGISTER

EFLAGS REGISTER

IT INDICATES THE CONDITION OF THE PROCESSOR AND HELPS TO CONTROL ITS OPERATION. IN ADDITION, THERE ARE BITS IN THE REGISTER THAT MAY BE REFFERED TO AS cintrol bits :

the x86 employs four control registers to control various aspects of processor operation. all of the registers except cr0 are either 32 bits or 64 bits long, depending on whether the implementation supports the x86 64-bit architecture. the cr0 register contains system control flags, which control modes or indicate states that apply generally to the processor rather than to the execution of an individual task. the flags are as follows:

INTERRUPT VECTOR TABLE

-trap flag (tf): when set,causes an interrupt after the execution f each instruction. this is used in debugging.

-interrupt enable flag (if): when set, the processor will recognized external interrupts.

-direction flag (DF): determines whether string processing instructions increment or decrement the 16-bit half-registers si and di or the 32-bit registers esi and edi.

this table contains 256 32-bit interrupt vectors, which is address ( segment and offset ) of the interrupt service routine for that interrupt number.

-i/o privilege flag (ipof): when set , causes the processor to generatean exception on all accesses to i/o devices during protected-mode operation.

-resume flag (RF): allows the programmer to disable debug exceptions so that th einstruction can be restarted after a debug exception without immediately causing another debug exception.

-alignment check (AC): activates if a word or doubleword is addressed on a nonword or nondoubleword boundary.

-identification flag (Id): if this bit can be set and cleared, then this processor supports the processor id instruction. this instruction provides information about the vendor, family, and model.

INTERRUPT HANDLING

-RECALL THAT THE FLOATING-POINT REGISTERS ARE TREATED AS A STACK FOR FLOATING-POINT OPERATIONS. FOR MMX OPERATIONS, THESE SAME REGISTERS ARE ACCESSED DIRECTLY.

-THE FIRST TIME THAT AN MMX INSTRUCTION IS EXECUTED AFTER ANY FLOATING-POINT OPERATIONS, THE FP TAG WORD IS MARKED VALID.THIS REFLECTS THE CHANGE FROM STACK OPERATION TO DIRECT REGISTER ADDRESSING.

-THE EMMS (EMPTY MMX STATE) INSTRUCTION SETS BITS OF THE FP TAG WORD TO INDICATE THAT ALL REGISTERS ARE EMPTY. IT IS IMPORTANT THAT THE PROGRAMMER INSERT THIS INSTRUCTION AT THE END OF AN MMX CODE BLOCK SO THAT SUBSEQUENT FLOATING-POINT OPERATIONS FUNCTION PROPERLY.

-WHEN A VALUE IS WRITTEN TO AN MMX REGISTER. THIS SETS THE VALUE IN THE FP REGISTER TO NaN (NOT A NUMBER) OR INFINITY WHEN VIEWED AS A FLOATING-POINT VALUE. THIS ENSURES THAT AN MMX DATA VALUE WILL NOT LOOK LIKE A VALID FLOATING-POINT VALUE.

Types of

Register Organization

JUST AS WITH A TRANSFER OF EXECUTION USING A CALL INSTRUCTION, A TRANSFER TO AN INTERRUPT-HANDLING ROUTINE USES THE SYSTEM STACK TO STORE THE PROCESSOR STATE.

INTERRUPTS AND EXCEPTIONS

TWO CLASSES OF EVENTS CAUSE THE x86 TO SUSPEND EXECUTION OF THE CURRENT INSTRUCTION STREAM AND RESPOND TO THE EVENT.

AN INTERRUPT IS GENERATED BY A SIGNAL FROM HARDWARE, WHILE AN EXCEPTION IS GENERATED FROM SOFTWARE.

* general : there are eight 32-bit general-purpose registers. these may be usedfor all types of x86 instructions;they can also hold operands for address calculations.

*segment : the six 16-bit segment registers contain segment selectors, the code segment (cs) register references the segment containing the instruction being executed.

*flags : the 32-bit eflags register contains condition codes and various mode bits.

*instruction pointer : cointains the address of the current instruction.

*numeric : each register holds an extended-precision 80-bit floating-point number.there are eight registers that function as a stack, with push and pop operations available in the instruction set.

protection enable

monitor coprocessor

emulation

task switched

extension type

numeric error

write protect

alignment mask

not write through

cache disable

paging

*cotrol : the 16-bit control register contains bits that control the operation of the floating-point unit, including the type of rounding control; single, double or extended precision; and bits to enable or disable various exception conditions.

*status : the 16-bit status register contains bits that reflect the current state of the floating-point unit, including a 3-bit pointer to the top of the stack; condition codes reporting the outcome of the last operation; and exception flags.

*tag word : this 16-bit register contains a 2-bit tag for each floating-point numeric register, which indicates the nature of the contents of the corresponding register.

The x86 processor family

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