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  • connecting hundreds of temporary registers to places where they’ll eventually be used eats up about half the power budget in a CPU.
  • solution to this problem is replacing the registers in a CPU with something called a ‘belt’
  • a weird combination of a stack and a shift register.
  • CPU can take data from any position on the belt, perform an operation, and places the result at the front of the belt.
  • No general registers or rename

registers >> fast, small, low-power bypass

  • No issue, dispatch, or retire stages

short pipe, low mispredict penalty

  • No encoded result addresses

compact code

  • Multi-result operations

Instructions and Pipelines

The Belt

Memory

  • a 64-bit Single Address Space (SAS) .

  • On-CPU caches all use virtual addressing

  • virtualisation is performed by a Translation Lookaside Buffer (TLB).

  • TLB allocate virtual memory in HW

The Belt

Introduction:

Mill CPU Architecture

  • The Mill is a new general-purpose

commercial CPU family.

  • Invented by Out-of-the-Box Computing.

  • This presentation from interview with Ivan Godard.

  • his group just knew they could "do better".

  • They worked for 10 years.

  • The Mill manages roughly 10% of the power

usage of other chips for the same

computations.

Metadata

Outline:

What is the Mill CPU?

Why it is different?

The belt.

Metadata

Memory

Instruction and pipeline

Instruction execution

References

  • Internal format

  • Vectorization

  • Pick

  • NaR

Advantages

Advantages:

  • Metadata reduces the number of distinct opcodes by a factor of seven.

  • Metadata enables speculative execution without fix-up code.

  • Metadata eliminates flag-control overheads in floating point.

  • Metadata permits vectorizing of

while-loops.

References:

Instruction and pipelines contd.

Mill has lots of pipelines, and each one issue an operation each cyle

  • ootbcomp.com

  • youtube.com

Thanks for listening

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