Send the link below via email or IMCopy
Present to your audienceStart remote presentation
- Invited audience members will follow you as you navigate and present
- People invited to a presentation do not need a Prezi account
- This link expires 10 minutes after you close the presentation
- A maximum of 30 users can follow your presentation
- Learn more about this feature in our knowledge base article
Do you really want to delete this prezi?
Neither you, nor the coeditors you shared it with will be able to recover it again.
Make your likes visible on Facebook?
You can change this under Settings & Account at any time.
LTE Physical layer Implementation
Transcript of LTE Physical layer Implementation
LTE physical layer
Conveys data and control information between EUTRAN Node B (e Node B) and user equipment (UE) in an efficient way.
Error correction techniques
Backward error correction (BEC)
For non real time application
Forward error correction (FEC)
For real time application
multicarrier modulation divides the wideband incoming data stream into L narrowband sub streams, each of which is then transmitted over a different orthogonal-frequency sub channel.
Physical Layer system
FPGA & VHDL
Field-programmable gate arrays (FPGA) are the modern-day technology for building a breadboard or prototype from standard parts, programmable logic blocks and programmable interconnects allow the same FPGA to be used in many different applications. For smaller designs and/or lower production volumes.
LTE Physical layer Implementation for transceiver
Mohamed Nagah Ali
Abdullah Mamdouh kishk
Ahmed Abdulrheem Mahmoud
Dr. Nariman Abdelsalam
The LTE downlink transmission scheme is based on
for LTE uplink transmission scheme is based
The uplink in LTE is based on orthogonal separation of users in time and frequency.
Multiple antenna support
can operate unpaired spectrum whereas
operate paired spectrum.
Range of Bandwidth
Bandwidth ranging from around 1.4MHz up to beyond 20MHz in steps of 180 kHz.
Generic frame structure
LTE frames are 10 m sec in duration.
They are divided into 10 sub frames, each sub frame being 1.0 m sec long.
Each sub frame is further divided into two slots, each of 0.5 m sec duration.
Slots consist of either 6 or 7 ODFM symbols, depending on whether the normal or extended cyclic prefix is employed .
Scalable Channel Bandwidth
Downlink transmission scheme
A resource block (RB) is a basic unit of access allocation.
RB bandwidth per slot (0.5 ms) is12 subcarriers times 15 kHz/subcarrier equal to 180 kHz.
Downlink reference signals
Downlink Physical Layer Processing
Not use memory
Parameters of Convolutional code
Block diagram Representation
Truth Table Representation
State Diagram Representations
Tree Diagram Representations
Trellis Diagram Representations
The encoder adds m (size of memory) dummy symbols at the end of the information sequence. This results in a loss in rate of the code.
Recursive Systematic Convolutional (RSC) Encoder
Obtained by feeding back one of its encoded outputs to its input
For data randomization
A high-rate stream of R bps is broken into L parallel streams, each with rate R/L and then multiplied by a different carrier frequency
A multicarrier modulation technique that has recently found wide adoption in a widespread variety of high-data-rate communication systems.
OFDM & OFDMA
The Discrete Fourier Transform (DFT) is the equivalent of the continuous Fourier Transform for signals known only at N instants separated by sample times T(i.e. a finite sequence of data).
We could regard each sample f [k] as an impulse having area f [k]. Then, since the integrand exists only the sample points
The Fast Fourier Transform
The time taken to evaluate a DFT on a digital computer depends principally on the number of multiplications involved, since these are the slowest operations. With the DFT, this number is directly related to N2 (matrix multiplication of a vector), where N is the length of the transform.
The DFT requires N2 complex multiplications. At each stage of the FFT complex multiplications are required to combine the results of the previous stage .since there are (log2N) stages, the number of complex multiplications required to evaluate an N-point DFT with the FFT approximately log2N .
Figure illustrates a typical FPGA architecture, There are three key parts of its structure: logic blocks, interconnect, and I/O blocks
Comparison between ASIC , Custom Processor ,FPGA ,and Generic.
channel coding transmitter
OVERALL System simulation
data format and encoderoutput
intearlever and SIPO output
4block of FEC output
PISO and deinterleaver output
From the rate 1/3 output of the turbo coder The rate matching block creates an output bit stream with a desired code rate. The function of this block is to add more security for the transmitted data and more immunity against the channel errors (RM) algorithm selects bits for transmission from the rate 1/3 turbo coder output via puncturing and/or repetition.
The sub-block interleaver reshapes the encode bit sequence, row-by-row, to form a matrix with CTC Subblock=32 columns and RTC Subblock rows .
For blocks d(0)k and d(1)k ,inter-column permutation is performed on the matrix to reorder the columns as shown in the following pattern. [0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31].
The output of the block interleaver for blocks d(0)k and d(1)k is the bit sequence read out column-by-column from the inter-column permutated matrix to create a stream Kπ=(RTC Subblock × CTCSubblock) bits long.
Bit Collection, Selection, and Transmission
The bit collection stage creates a virtual circular buffer by combining the three interleaved encoded bit streams.
The circular buffer is the most important part of the rate matching module, making puncturing and repetition of the mother code possible . For any desired code rate the coded bits are output serially from the circular buffer from a starting location, given by redundancy version (RV) which points to different locations of the circular buffer.
Circular-buffer rate matching
The downlink data modulation transforms a block of scrambled bits to a corresponding block of complex modulation symbols.
The set of modulation schemes supported for the LTE downlink includes QPSK, 16QAM and 64QAM, corresponding to two, four, and six bits per modulation symbol, respectively.
In this project, a LTE base band transceiver has been designed with some modifications to fit in the utilization on FPGA kit. All the stages of modified LTE physical layer including transmitter and receiver are modeled using Xilinx® ISE® Design Suite version 14.2 and implemented on Spartan 3E XC3S500E FPGA kit. The implemented blocks are channel coding and OFDM for both transmitter and receiver. Finally, the result of this project is a modified prototype of LTE physical layer.
Future work is aimed to implement the full LTE physical layer including the downlink and uplink scenarios with release 9. To achieve this, a different FPGA kit family may be used. Furthermore, a good enhancement can be done with the LTE-advanced starting with Release 10 Specifications.
v(1)k and v(2)k are combined by interlacing successive values of v(1)k and v(2)k to create the circular buffer wk. shown in figure .
Hard-Decision Viterbi Algorithm:
Let Message sequence = [1 0 1 0 1].
Thus, Code sequence = [11 01 11 00 11]
And, Received sequence = [11 01 01 00 11]
The decoding steps:
Branch Metric Calculation
Add, compare and select the survivor path
Trace Back the survivor path
Decoding the algorithm
Branch Metric (BM) Calculation:
Add, Compare and Select (ACS) the survivor path:
Add, Compare and Select (ACS) the survivor path:
Trace Back (TB):
Note that an m-zero bits added to the received sequence to go back to Sa with the minimum metric.
Decoding the received sequence:
From the trellis diagram, the corrected sequence is:
Thus the decoded sequence is: