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Virtual Platform Based Design of an Embedded Option Pricing

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Jose Cubero

on 10 April 2014

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Transcript of Virtual Platform Based Design of an Embedded Option Pricing

Virtual Platform Based Design of an Embedded Option Pricing System on the Xilinx Zynq-7000 AP SoC
By Jose Cubero
Results &

Simulation Time & Model Accuracy
Efficient Option Pricing
Estimation of the price of an asset in time.
Needed for risk assessment.
Fundamental task in financial institutes.
Model complexity, tight constraints.
Compute intensive -> High Energy Cost.
Virtual Platform Methodology
SW Model that emulates a real platform.
Fast simulation environment.
No need for HW prototype.
Early SW development.
HW/SW integration and exploration.
Enhanced visibility.
ISS: Instruction Set Simulators.
Peripheral Models: C/SystemC (IEEE-1666-2011).
TLM2 (OSCI 2009) used as "glue" code.

Tool Selected:
Cadence Virtual System Platform (VSP).
Zynq platform model ready to be used.
Xilinx Zynq-7000 AP SoC
Innovative silicon device. (Released in March, 2011).
ARM based MP, efficient OCM, standard peripherals.
28nm FPGA.

Robust and Flexible.
Unrivaled HW/SW bandwidth.
Low power.

Processor centric. (Standard ARM dev.)
Reconfigurable FPGA.
Advanced intra-chip interconnections.
Written in SystemC
Implements the Algorithm
HW/SW split is explicit.
Abstract Channel.
APU (ARM Cortex A9)
Memory (On-chip & External)
PL: (Varies with chip model)
Logic cells, BRAMs, DSP.

PS-PL interfaces:
General Purpose (2x AXI_M & 2 xAXI_S)
High Performance (4x AXI_S)
Accelerator Coherent (1x AXI_S)
Other (Not bus-based): Interrupts, DMA, Debug, configuration.
AXI Streaming FIFO:
Vivado HLS

Heston MLMC Kernel:
Custom Design
Memory mapped registers
Parameters (RW)
Status (RO)
Command (WO)

Synchronization Protocol
Handshake between SW and HW
Functionality not changed.

TLM2 target sockets for AXI slave ports
sc_fifo channel for the AXI-4 stream
Events and methods for synchronization.

Automatic generation (TLMGen):
Register description file as input.
Generates TLM2 target socket &
Register bank.

Bare-metal or OS?

File System
Ubuntu Core

Interface Adaptation
User space driver (via
Custom HW/SW interface

Binary generation
Cross Compilation (Xilinx toolchain)

Test Bench components:
Zynq PS: OVP + peripherals
Board Level Peripherals
Zynq PL: Custom HW Acc.

Memory Map
Config file
SW binaries
SD Card Image
Platform Constraints
Reference Model
HW/SW Interface (Logical)
System Architecture
SW Adaptation
HW Model Adaptation
Virtual Platform
Simulation Results
Simulation Flow
- Compilation and elaboration
- Linux Boot
- Connect though
- Run SW binaries as in the real board.

HW/SW IF Debug
- Console messages

Model Accuracy
Custom HW was not ready. HLS implementation used for comparison.
The same set of parameters in both the Zedboard and the VP.
Accomplishments & Learnings
Future Work
Designed of a custom HW/SW interface.

Constructed TLM2 models for 3 different IP cores.

Implemented a realistic Virtual Platform.

Explored the Cadence VSP tool suite.

Explored the dev. flow for Embedded Linux on the Zynq-7000 AP SoC.
Improvements to the HW/SW Interface
Interrupts, HP/ACP port, DMA...

Further Tool Exploration and Porting of the Project
New version of Cadence VSP available (02.14).
Migration to Synopsys PA.

Support of HW Re-Configurability
How can we model it in SystemC?
SystemC HLS Flow
Use the VP models for HW synthesis.
Improved algorithms. & efficient HW architectures.

Reference and scope:
FPGA HW acceleration. (de Schryver, Torruella, Wehn. March 2013.)
European barrier options. MLMC in the Heston Model.
Time Accuracy
Arithmetic Accuracy
Simulation Time:
Simulation Time
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