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SAP 1

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by

Verlyn Lingo

on 10 June 2014

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Transcript of SAP 1

Architecture
Instruction Set
Binary Pattern designed
Instruction Set - Basic Operation
LDA
ADD
SUB
OUT
HALT
Memory Reference Instruction
Memory
Reference
Instruction
Mnemonics -> Operation
LDA
Programming
SAP-1
Machine Cycle & Instruction Cycle
SAP 1




SAP 2
GOAL!
SAP 1
Simple As Possible 1
Ma. Cristina Jennie
Isabel Glen Verlyn Julius
perform
specific task
Instruction
supports
entire group
each
represented
8-bit
Binary
valve
OP code or
Instruction
Byte
called
Load the
accumulator
INCLUDES
THE ADDRESS OF
THE WORD TO
BE ADDED

INCLUDES THE HEXADECIMAL ADDRESS OF THE DATA LOADED.

LDA
INCLUDES THE
ADDRESS OF
THE WORD
TO BE
SUBTRACTED
TRANSFER
THE ACCUMULATOR
CONTENTS TO
THE OUPUT PORT

TELLS THE COMPUTER TO STOP PROCESSING DATA

LDA
ADD
SUB
used
stored
OUT
HLT
ADD
SUB
OUT
HLT
Accumulator
Load RAM Data
into
to
from
data
output
register
into
stop processing

Program Counter
counts from 0000
1111
its job is to
memory address of the next instruction
to be fetched and executed.
Input and MAR
Includes the address & data
switch registers
Send 4 address bits &
8 data bits to the RAM

RAM
16 x 8 STATIC TTL RAM
This allows us to store a program
and data in the memory before a
computer run.
INSTRUCTION REGISTER
part of the control unit
composed of
OPCODE
ADDRESS
content
split
in to two
UPPER NIBBLE
LOWER NIBBLE
ACCUMULATOR
Is an 8 bit buffer register that
stores intermediate answers
during computer run.
also defined as Register
ADDER-SUBTRACTOR
This block takes inputs form Accumulator and/or other registers
Perform arithmetic operation
in microprocessor
Asynchronous
Register
Is the register used to store 8-bit data for the operation
used in
arithmetic
operation
Controller-
Squencer
is the
signal
controlling
&
sequencing
unit.

Generates signal for each block so
that action occur in desired sequence.

OUTPUT
Register
often called
OUTPUT PORT
Holds the output of
the
OUT
instruction

BINARY DISPLAY
Each LED connects to
1 flip-flop (FF) of the
Row of 8 LEDs
CONTROL
UNIT
Program Counter
Instruction Register
Controller-Squencer
ALU
Accumulator
B
REGISTER
ADD /
SUB
RAM
MAR
MEMORY
UNIT
INPUT AND OUTPUT UNIT
INPUT
PROGRAMMING
SWITCHES
OUTPUT
PORT
To load instruction and data words into the SAP-1 memory
code
interpret
w/c
operation
to perform
called
OP CODE
operation
code
Assembly Language
Involves working with
mnemonics when writing
a program.
The original program with
mnemonics is called a
Machine Language
SOURCE PROGRAM
Involves working with
strings of 0s and 1s.
Any program written in
machine language is
OBJECT PROGRAM
Assembly Language
& Machine Language
Instruction Field & Address Field
The four MSBs of a SAP-1 machine language instruction specify the operation, and the four LSBs give the address.
We refer to the MSBs as the instruction field and
to the LSBs as the address field. Symbolically,

Instruction = xxxx xxxx
CHUNK
Chunk the program and data in machine language by converting to hexadecimal shorthand.
This version of the program and data is still considered machine language.
Incidentally, negative data is loaded in 2’s compliment . Example: -03 is entered as FDH.

Control Unit
automatic
operation
generates the
CONTROL WORDS
that
Fetch &
Execute
instruction
passes
diff.
timing states
T states
periods during w/c register contents change
Ring counter
RING COUNTER
->output
ring word
T = 000001
T = 000010
T = 000100
T = 001000
T = 010000
T = 100000
each ring word rep.one T state
clock
&
timing pulses
produces 6 states
FETCH CYCLE
T1
T2
T3
T1
Address State
because
Program
Counter
MAR
Memory
Address
Register
T2
Increment State
Program
Counter
incremented
T3
Memory State
RAM
IR
instruction register
transferred from
Execution Cycle
T4 , T5 , T6
The register transferred during execution
cycle depend on the particular instruction being executed

LDA
ROUTINE
T4
T5
T6 Nop
ADD & SUB Routine
T4
LDA
T5
T6
OUT Routine
T4
HLT
Control
routine
no register
are involved
IR = 1111 XXXX
Full transcript