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SAP1(Simple-As-Possible) Computer

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elianjon duarte

on 9 September 2014

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Transcript of SAP1(Simple-As-Possible) Computer

Introduction to Sap-1
SAP-1 stands for simple as possible computer
SAP-1 is a computer made from discrete IC’s
4 address lines
Can handle max. of 16 address locations
Instruction set includes instructions

LDA 0000
ADD 0001
SUB 0010
OUT 1100
HLT 1111

Complete code includes opcode and operand

Like LDA 04H 0000 0100

One instruction is executed in one instruction cycle

Machine Cycle/Instruction Cycle
Instruction cycle may consist of many machine cycles
For SAP-1, Instruction cycle= machine cycle
Instruction cycle=Fetch cycle+Execution Cycle
Fetch cycle is generally same for all instructions

SAP1(Simple-As-Possible) Computer
To load the instruction and data words into sap-1 memory we have to use some kind of code that the computer can interpret.the number 0000 stands for LDA , 0001 for ADD, 0010 for SUB 1110 for OUT , and 1111 for HLT. Because this code tells the computer which operation to be perform, it is called an operation code (op code).
Program Counter
The program is stored at the beginning of the memory with the first instruction at binary address 0000, the second instruction at 0001, the third at address 0010 and so on. The program counter which is part of the control unit, counts from 0000 to 1111. Its job is to send to the memory the address of the next instruction to be fetched and executed. It does this as mentioned in the next paragraph.
Input & MAR
The Input and MAR includes the address and data switch registers. Switch registers are part of input unit, allows us to send 4 address bits and 8 data bits to the RAM.
The memory address register (MAR) is the part of SAP-1 memory. During a computer run, the address in the program counter is latched in to the MAR. A bit later, the MAR applies this 4-bit address to the RAM where a read operation is performed.
The RAM is a 16 X 8 static TTL RAM. We can program the RAM by means of the address and data switch registers. This allows you to store a program and data in the memory before a computer run.
During a computer run, the RAM receives 4-bit addresses from the MAR and a read operation is performed. In this way, the instruction or data word stored in the RAM is placed on the W bus for use in some other part of the computer.
Instruction Register
The instruction register is the part of the control unit. To fetch an instruction from the memory the computer does a memory read operation. This places the contents of the addressed memory location on the W bus. At the same time, the instruction register is set up for loading on the next positive clock edge. The content of the instruction register are split into two nibbles. The upper nibble goes directly to the block “Controller – Sequencer”. The lower nibble is read onto the W bus when needed.
Controller – Sequencer
Before each computer runs, a CLR signal is sent to the program counter and CLK signal to the instruction register. This resets the program counter to 0000 and wipes out the last instruction in the instruction register.
A clock signal CLK is sent to all buffer registers; this synchronizes the operation of the computer ensuring that things happen when they are supposed to happen.
The 12 bits that come out of the controller sequencer form a word controlling the rest of the computer (like a supervisor telling others what to do). The 12 wires carrying the control word are called the control bus. The control word has the format of: CON = CP EP LM CE L1 E1 LA EA SUEULBLO
This word determines how the registers will wait to the next positive CLK edge. For example, a high EP and a low LM means that the program counter are latched into the MAR on the next positive clock edge. As another example, a low CE and a low LA means that the addressed RAM word will be transferred to the accumulator.
The accumulator (A)
is a buffer register that stores intermediate answers during a computer run. Accumulator has two outputs, one directly goes to the adder-subtractor and the other goes to the W bus.

The Adder – Subtractor
SAP-1 uses a 2’s complement adder-subtractor. When SU is low, the sum out of the adder-subtractor is S = A + B. When SU is high, the difference appears as A = A + B ’.
B Register
The B register is another buffer register. It is used in arithmetic operations. A low LB and positive clock edge load the word on the W bus into the B register. The two state output of the B register drives the adder-subtractor, supplying the number to be added or subtracted from the content of the accumulator.
Output Register
At the end of the computer run, the accumulator contains the answer to the problem being solved. At this point, we need to transfer the answer to the outside world. This is where the output register is used.
When EA is high and LO is low, the next positive clock edge loads the accumulator content to the output register. The output register is often called an output port because the processed data can leave the computer through this register.
Binary Display
The binary display is a row of eight light emitting diodes (LED’s). Because each LED connects to one flip-flop of the output port, the binary display shows us the content of the output port. Therefore, after we transferred an answer from the accumulator to the output port, we can see the answer in binary form.
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Duarte And Atendido
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