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SHMACsim progress presentation - 05.04.2013
Transcript of SHMACsim progress presentation - 05.04.2013
heterogeneity: integer or FP MIPS cores
memory: distributed, non-coherent
msg routing: simple x-y routing, while stalling cores
can we do it? yes!
but many questions remain unanswered Why do we need the SHMAC? EECS wants energy efficiency
EECS wants to use heterogeneity for energy efficiency research
need a platform to experiment with, find answers
...on various levels of abstraction SHMACsim (can) reflect the SHMAC prototype
easy to use, maintain
swappable blocks with clean interfaces
internalizing implementation details
allow modelling on different abstraction levels
have a library of useful tiles (RAM, sync, MIPS cores...) to speed up prototyping - background, status, plans SHMACsim how best to use accelerators? how to schedule tasks, resources? how to choose cores/resources/interconnect? how to make the blocks, and make them work together? how to make the blocks energy efficient? existing platforms cannot answer (all) these questions what kind of cores? which ISA? routing? memory system? cache coherence? interconnect? accelerators? the heterogeneous design space is huge
need to evaluate options, combinations, parameters with ease
VHDL and FPGA powerful, but takes time solution: SHMACsim hw synchronization? Requirements: The "Virtual Heterogeneous Multicorn" SystemC model of SHMAC
aims to simulate the SHMAC prototype (and beyond)
initiated Feb 2013 as a MSc project SHMAC? Single-ISA Heterogeneous Multicore Architecture Computer
mesh of heterogeneous tiles
tiles could be
slow CPU cores
fast CPU cores
prototype on FPGA built last year The "Heterogeneous Multicorn" by Yaman Umuroglu
presented at CARD group meeting 05.04.2013 Future Work &
Discussion cycle-accurate simulation
improvements to SHMAC arch Current Status behavioral model is ready
MIPS-I cores, w/ MIPS-II LL/SC instructions
LL/SC tile for synchronization
"magic" routers (infinite bandwidth, zero delay) Demo time! SystemC:
SHMACsim simulation infrastructure IEEE standard for system-level and transaction-level modeling
In practice, SystemC is a C++ class library that offers:
discrete event-driven simulation kernel
explicit concepts of time and concurrency
modeling on different abstraction levels Levels of SystemC modeling high-level modeling already possible in C++
SystemC also offers HDL-like capabilities for RTL(ish)* modeling
delta cycles, sensitivity lists, signals..
possible to mix the two for performance + accuracy *an explicit "synthesizable SystemC subset" is in the works Time and Concurrency print module name and
current simulation time pass time (=yield & reschedule after m_wait nanoseconds simulated time) declare the "run" function as a SystemC thread (always running process without a sensitivity list) 1. Declaring a SystemC module 2. Instantiating modules and starting the simulation 3. The output, observe passage of time and concurrency ArchC:
SHMACsim core generation ArchC is a Processor Description Language
Given an ISA, it generates a SystemC processor model (functional or timed)
mature (SPEC 2000'd) SystemC models for MIPS-I, PowerPC, SPARC-V8, ARMv5, 8051..
syscall emulation, TLM memory port
some modifications for SHMAC needed (mem mapping) SystemC model
+ GNU bintools acsim Thank you for listening! cache? coherency? multiple/heterogeneous interconnects? coherent memory as an allocatable resource? single ISA? accelerators?
database accelerator? simulated power measurements? integrating GEM5 cores?