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Structure and Role of the Processor

for AQA AS Computing section 7.2

Linda Davies

on 7 November 2012

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Transcript of Structure and Role of the Processor

SIMPLIFIED INTERNAL STRUCTURE OF A PROCESSOR Main Processor Components Processor Program Control Unit Program Control Unit – fetches instruction from memory, decodes and executes 1 at a time Arithmetic & Logic Unit Arithmetic & Logic Unit – performs operations on data – Arithmetic, Floating Point, Boolean Internal Clock Internal Clock – based on system clock – usually adjusted to reach Processor speed by frequency-multiplying circuits inside the processor Internal Buses Internal Buses – linking Control, ALU and Registers Logic Gates Logic Gates – used for flow control Registers Registers – fast Memory locations inside the Processor (or I/O) – they may be GENERAL-PURPOSE (available for programmer) or Dedicated DEDICATED REGISTERS in the Processor SP SP – Stack Pointer - holds return addresses & parameters when subroutines are called - it is found near the end of the General-Purpose Registers PC PC – Program Counter – points to the next instruction to be fetched & executed SR SR – Status Register – holds code flags, e.g. zero, negative, overflow, interrupt ACC ACC – Accumulator – holds result of calculations, e.g. add number to ACC & store – usually the first of the General-Purpose Registers CIR CIR – Current Instruction Register – holds an instruction while it is decoded & executed MAR MAR – Memory Address Register – holds address of current memory location MBR MBR – Memory Buffer Register – holds the data currently being transferred to MAR Control Bus Address Bus External (System) Bus Data Bus System
Clock Control
Circuits Instruction
Decoder Control
Signals Arithmetic & Logic Circuits Data R1-R7 System Clock & Clock Speed All computers have a quartz-controlled oscillator – used for timing operations at a fixed rate All timing signals are derived from this – they regulate & synchronise operations of P, MM, I/O Processors are designed to work at specific clock speed – number of ticks per operation Rate / Speed / Frequency measured in GHz or MHz – doubles every year approx. Clock Frequencies over time: 1986: 10MHZ, 1994: 100MHz, 2002: 1GHz, 2012: ?? Processor Performance Word Length – number of binary digits in a BINARY WORD – used for all data / instructions BUS WIDTH – number of wires in a bus = word size (each wire = 1 signal = 1 bit) PERFORMANCE is measured in number of MACHINE OPERATIONS per second (OPS)
GOPS = Giga-Ops (10^9)
MOPS = Mega-Ops (10^6) Effect of Clock Speed on Processor Performance Clock Speed x 2 = program execution x 2 Doubling the CLOCK SPEED makes the processor execute instructions twice as fast, as each MACHINE CODE instruction is executed in 1 Clock Tick or Cycle (HZ=Cycles per second) LIMIT on clock speed – faster the chip operates, the more HEAT is generated – processor dies Effect of DATA Bus Width on Processor Performance Bus Width x 2 = program execution x 2 Bus width = the amount of data the CPU can transmit at a time to main memory and to input and output devices (bits per cycle) e.g. an 8-bit bus moves 8 bits of data at a time.  Bus width can be 8, 16, 32, 64, or 128 so far Bigger number = faster transfer of data Effect of Word Length on Processor Performance Word size - a binary word is the amount of data the CPU can process at one time (bits per cycle) e.g an 8-bit processor can manipulate 8 bits at a time Bigger the number = faster processing It also affects the range of numbers that can be handled - Greater Word Length allows more complex maths Effect of ADDRESS Bus Width on Processor Performance Moore’s Law deviation Reason for Moore’s Law breaking down:
packing in more transistors on a chip increases power consumption and outputs more heat How to overcome this?
MULTI-CORE = more than 1 Processor on a chip – called CORES – run at lower frequency, use less power and can perform multiple tasks – also useful for Multi-Media A wider Address Bus does not directly affect performance However, a wider address bus allows a longer word length This means more memory can be addressed The limitation is that the Registers (PC, MAR) must also be able to accommodate the longer word length (32 / 64 bits) Bigger the number = more RAM addresses Limitation - if word size too big for ACC - processing gets slower as results have to be split over several Registers Also – if CIR is not big enough to hold the instruction – the system Bus must be used again –slower processing
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