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Overview of PCI(e) Subsystem

Introduction to Linux PCIe Subsystem
by

kishon ivp

on 21 October 2016

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Transcript of Overview of PCI(e) Subsystem

OVERVIEW OF PCI(e) SUBSYSTEM
KISHON VIJAY ABRAHAM I, VIGNESH R
Introduction
PCIe Vs PCI
Usage model and software interface same as PCI
Serial communication interface like USB, SATA
Performance: Higher throughput, multi-lane
Add peripherals to the system (USB, Ethernet, SATA, DCAN etc..)
SoC
Root Complex
Topology
Terminology
Root Complex - PCIe host
Endpoint - PCIe device
cpu_addr - CPU physical address (proc/iomem)
pci_addr - PCI bus address
Switches - allow more devices to be connected
I/O Lines
Address Space
0
2 - 1
32/64
4Kb
4Kb
4Kb
Memory address (PCIe address space) determines configuration register accessed
Function of bus number, device number, function and register number
Bus Number
Device Number
Function
Number
Extd. Register
Number
Register Number
Size
0
2
8
12
15
20
Device Tree
pcie1: pcie@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <
A
0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
interrupts = <0 232 0x4>, <0 233 0x4>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x82000000 0
C C
0 0xfffd000>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 1>,
<0 0 0 2 &pcie1_intc 2>,
<0 0 0 3 &pcie1_intc 3>,
<0 0 0 4 &pcie1_intc 4>;
pcie1_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
Controller Configuration
HW initialization
enabling clocks
Driving Reset Lines
PHY programming
IP initialization
ATU programming
Read/Write ops for configuration space
Lanes
pci-exynos
pci-mvebu
pci-imx6
pci-mvebu
pci-dra7xx
PCIE Driver
(drivers/pci/host/)
(arch/arm/kernel/
bios32.c)
PCI CORE
(drivers/pci/)
r8169
xhci-pci
ahci
sdhci-pci
tg3
Linux PCI(e) Subsystem
DOMAIN STACK
Other Plat
PCI BIOS
Other Arch
RX+
RX-
TX+
TX-
REFCLK+
REFCLK-
PERST#
WAKE#
PRSNT1#
PRSNT2#
JTAG#
+12V#
RX+
RX-
TX+
TX-
Host Bridge
PCI Express
Endpoint
Switch
Virtual PCI-PCI
Bridge
SoC
Configuration Space
Backward compatible with PCI Specification
Every function has a configuration space
Type0 - Endpoint; Type1 - Bridges, Rootports, switches
Class code - Differentiating Type
Device Info - Vendor id, Product id and Capabilities
Device Configuration - BAR, PM
4Kb
100000h
Bus:1 Device:0 Function:0
PCI Express
Endpoint
PCI Express
Endpoint
PCI Express
Endpoint
PCI Express to
PCI/PCX Bridge
PCI Express
Endpoint

PCI/PCX
CPU
Memory
Virtual PCI-PCI
Bridge
Virtual PCI-PCI
Bridge
Virtual PCI-PCI
Bridge
Virtual PCI-PCI
Bridge
Virtual PCI-PCI
Bridge
Virtual PCI-PCI
Bridge
Virtual PCI-PCI
Bridge
Root Complex
Configuration
Space
IP Registers
Configurable
Address
Space
CPU
Memory
4Kb
PCIe Endpoint
Memory Space
PCIe Address
Space

Device Id
Vendor Id
x x x x x x x x x x x x x x x x x x x x x x x x x x x
Status
Command
Class Code
Revision Id
BIST
Header Type
Lat. Timer
Cache Line S.
Base Address Registers
Cardbus CIS Pointer
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address
Reserved
Cap. Pointer
Reserved
Max. Lat
Min. Gnt
Interrupt Pin
Interrupt Line
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
4Kb
Configuration Space Header
27
4Kb
Configuration
Space
PCIe Bridge
4Kb
Bus:2 Device:0 Function:0
200000h
4Kb
Configuration
Space
PCIe Endpoint
Memory Space
4Kb
Bus:4 Device:0 Function:0
400000h
CFG0
CFG1
4Kb
4Kb
Source
Address
Destination
Address
Size
Type
A
A
<ECAM>
4Kb
CFG0
0
00
1
0 = Memory Request
1 = IO Request

00 = 32-bit Address Decoding
10 = 64-bit Address Decoding

1 = pre-fetchable
0 = non pre-fetchable
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
B
64Kb
IO
~
256MB
MEM
X
Y
<SIZE FROM BAR>
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
C
C
256MB
MEM
C
X
Y
Z
1GB MEM ADDR
1GB
1GB
'ranges' Property
Source
Address
Destination
Address
Size
Type
#address-cells = <3>;
#size-cells = <2>;
ranges = <
0x
82
000000
0
C C
0 0xfffd000>;
0
2 - 1
32/64
PCIe Address
Space
PCI Address
CPU Address
Size
CPU
PCIE
C
C
~256MB
MEM
Z
Interrupts
SoC
Root Complex
CPU
Memory
4Kb
Configuration
Space
PCIe Endpoint
Memory Space
4Kb
Configuration Space Header
1GB
Interrupt
Controller
Assert_INTx
Deassert_INTx

Capability ID
Next Pointer
Message Control
Message Address
Message Data
Write Message Data
to Message Address

Legacy
MSI
0 = INTx Not used
1 = INTA#
2 = INTB#
3 = INTC#
4 = INTD#
s s
0 0 0
t
p
n
01: I/O Space
10: 32 bit Memory Space
11: 64 bit Memory Space
prefetchable (cacheable)
relocatable
Interrupt Handling
tg3
xhci-pci
ahci
TG3
USB-PCI
SATA-PCI
Root Complex
Interrupt
Controller
3
1
2
4
5
request_irq(3)
request_irq(3)
request_irq(3)
(VIRT)IRQ 3
Root Complex
Driver
SW
HW
IRQ 3
request_irq(3)
(VIRT)IRQ 3
(VIRT)IRQ 3
request_irq(6)
request_irq(7)
request_irq(8)
(VIRT)IRQ 6
(VIRT)IRQ 7
(VIRT)IRQ 8
generic_handle_irq(6)
generic_handle_irq(7)
generic_handle_irq(8)
lspci
root@am57xx-evm:~# lspci
00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01)
01:00.0 PCI bridge: Pericom Semiconductor Device 2304 (rev 05)
02:01.0 PCI bridge: Pericom Semiconductor Device 2304 (rev 05)
02:02.0 PCI bridge: Pericom Semiconductor Device 2304 (rev 05)
03:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01)
04:00.0 USB controller: Etron Technology, Inc. EJ168 USB 3.0 Host Controller (rev 01)
Displays all PCI buses, devices in a system
http://linuxcommand.org/man_pages/lspci8.html
Acknowledgements
Jingoo Han, Pratyush Anand, Bjorn Helgaas, Arnd Bergmann, ...
Linux Community
Texas Instruments
References
PCI Local Bus Specification 3.0
PCI Express Base Specification 3.0
PCI Express System Architecture (by Mindshare)
Linux Foundation
Happy Hacking!
Feedback:
kishon@ti.com
kishonvijayabraham@gmail.com


vigneshr@ti.com
vigneshrblr@gmail.com

BUS 0
BUS 1
BUS 3
BUS 9
BUS 4
BUS 4
BUS 5
BUS 6
BUS 7
BUS 8
BUS 2
Device 0
Device 0
Device 0
Device 0
Device 0
Device 0
Device 0
Device 1
Device 2
Device 3
Device 4
Configuration
Space
X
1) read BAR = 0xFFF00008

2) Clear last
4 bits = 0xFFF00000

3) Invert the
bits = 0x000FFFFF

4) Add '1' = 0x100000

1MB
Device Id
Vendor Id
x x x x x x x x x x x x x x x x x x x x x x x x x x x
Status
Command
Class Code
Revision Id
BIST
Header Type
Lat. Timer
Cache Line S.
Base Address Registers
Cardbus CIS Pointer
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address
Reserved
Cap. Pointer
Reserved
Max. Lat
Min. Gnt
Interrupt Line
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
0
00
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
X
1
C
D
E
D
E
Enhanced Configuration Access
Mechanism (ECAM)
Configurable
Address
Space
CFG0
CFG1
4Kb
4Kb
A
B
64Kb
IO
~
256MB
MEM
X
Y
<SIZE FROM BAR>
C
D
E
C
X
Y
Z
D
E
BUS 3
Full transcript