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VHDL AMS Case Study 1 Mixed-Signal Focus

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saeed ezzati

on 21 May 2010

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Transcript of VHDL AMS Case Study 1 Mixed-Signal Focus

VHDL AMS
Case Study 1
Mixed-Signal Focus The case studies explore the design of a radio-controlled (RC),
electric-powered air- plane system. Case Study 1: Mixed-Signal Focus
The first case study focuses on
encoding,
transmission
and decoding of command signals

we emphasizeAnalog-to-digital and digital-to-analog signal conversions to illustrate mixed-signal modeling with VHDL-AMS. Command and Control System Design analog control (the control stick blocks) digitization and encoding(the digitize/encode block) decoding and pulse-width generation (the decode/PW block) pulse-width-to-analog voltage conversion (the PW/analog blocks) The control sticks output continuous analog signals whose values are derived from the position of a mechanical lever with which the operator controls the airplane. move vertically : control the speed of the plane.
move horizontally : control the direction. outputs of the control stick vary from 0 V to 4.8 V the control lever center position corresponds to 2.4 V on the output. = one-half of its maximum speed. down : decrease speed
up : increase speed Control Sticks proffesor : Dr. eshghi

presented by : saeed ezzati sample the analog outputs of the two control sticks every 20 ms and convert them into 10-bit serialized digital strings. Digitize/ Encoder Data is organized in the bitstream as a collection of frames, each of which is 20 ms in duration. Each frame consists of up to 8 channels, each about 2 ms in duration. The minimum allowable data rate for this system is
(8 channels) x (16 bits/channel) / (20 ms frame length) = 6400 bits/s. The meaningful data for the system is contained in the first three channels of the frame: synchronization, throttle and rudder; Each channel is 16 bits: 10 data bits, 1 start bit and 1 parity bit. Additionally, 4 zero bits are added to the end of each channel to provide clear channel separation when we view waveforms. library ieee; use ieee.std_logic_1164.a11;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity a2d_nbit is
port ( signal start'in std_ulogic; - - Start signal
signal clk 9 in std_ulogic; - - Strobe clock
terminal ain 9 electrical; - - A n a l o g input terminal
signal eoc" out std_ulogic := '0'; - - E n d of conversion pin
signal dout 9 out std_ulogic_vector(9 downto O) ); - - Digital output signal
end entity a2d_nbit;

---------------------------------------------------------------
architecture sar of a2d_nbit is
constant Vmax" real := 5.0; - - A D C ' s m a x i m u m range
constant delay'time := 10 us; - - A D C ' s conversion time
type states is (input, convert); - - Two states of A2D Conversion
constant bit_range 9 integer := 9; - - Bit range for dtmp and dout
quantity Vin across lin through ain to electrical_ref; - - ADC's input branch
begin
sa_adc: process is
variable thresh 9 real := Vmax; - - Threshold to test input voltage against
variable V t m p " real := Vin; - - Snapshot of input voltage
- - when conversion starts
variable dtmp 9 std_ulogic_vector(bit_range d o w n t o 0); - - Temp. output data
variable status 9 states := input; - - Begin with "input" case
variable bit_cnt 9 integer := bit_range;
begin
case status is
when input => - - Read input voltages when start goes high
wait on start until start = '1' o r start = 'H';
bit_cnt := bit_range; - - Reset bit_cnt for conversion
thresh "= Vmax;
Vtmp := Vin; - - Variable to hold input comparison voltage
eoc <= '0" - - Reset end of conversion
status := convert; - - Go to convert state
when convert => - - Begin successive approximation conversion
wait on clk until clk = '1' or clk = 'H';
thresh "= thresh / 2,0; - - Get value of MSB
if Vtmp > thresh then
dtmp(bit_cnt) := '1'; - - Store '1'in dtmp variable vector
Vtmp := Vtmp - thresh; - - Prepare for next comparison
else
dtmp(bit_cnt) := '0'; - - Store '0' dtmp variable vector
end if;
if bit_cnt > 0 then
bit_cnt := b i t _ c n t - 1; - - Decrement the bit count
else
dout <= dtmp; - - Put contents of dtmp on output pins
eoc <= '1' after delay; - - Signal end of conversion
status := input; - - Go to input state
end if;
end case;
end process sa_adc;
lin == 0.0; - - Ideal input draws no current



end architecture sar; Decoder/Pulse-Width The decoder/PW block receives an asynchronous TDM digital bitstream from the
encoder block via the RF transmit/receive block. The data is synchronously extracted from the TDM bitstream and converted into parallel words representing the original digitized control-stick information. convert the analog pulse-width information from the decoder/PW block into analog voltage signals. The incoming pulses are converted into digital words (again using digital counters), and these words are transformed into their analog equivalents using digital-to-analog (D/A) converters. thanks for your attention pulse-width to analog
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