Loading presentation...

Present Remotely

Send the link below via email or IM


Present to your audience

Start remote presentation

  • Invited audience members will follow you as you navigate and present
  • People invited to a presentation do not need a Prezi account
  • This link expires 10 minutes after you close the presentation
  • A maximum of 30 users can follow your presentation
  • Learn more about this feature in our knowledge base article

Do you really want to delete this prezi?

Neither you, nor the coeditors you shared it with will be able to recover it again.


FPGA Technology for Test Applications

Using FPGA-based hardware to enhance and enable new test applications

Christian Hahn

on 30 April 2010

Comments (0)

Please log in to add your comment.

Report abuse

Transcript of FPGA Technology for Test Applications

FPGA Technology Consists of three main parts Why are they useful in general? True Parallelism – Provides parallel tasks and pipelining High Reliability – Designs become a custom circuit High Determinism – Runs algorithms at deterministic rates down to 25 ns
(faster in many cases)
Reconfigurable – Create new and alter existing task-specific personalities
FlexRIO Features Peer-to-peer streaming
800 MB/s across PXI Express backplane
16 simultaneous streams
Onboard DRAM
2x 256 MB banks
1.6 GB/s per bank
Enhanced Synchronization
Share PXI 10 MHz reference clock or DSTAR_A with adapter module PXI PXI Express Virtex-5 FPGA
LX30, LX50, LX85, LX110
Direct access to FPGA I/O
132 single-ended lines or 66 differential pairs
400 Mbps single-ended
1 Gbps differential
128 MB onboard DRAM
2x 64 MB banks
800 MB/s per bank
Adapter module required for IO Compact RIO Compact Vision System R-Series DAQ Single Board RIO FlexRIO 100 MHz maximum clock rate
54 single-ended digital I/O channels
Selectable voltages of 1.8, 2.5, and 3.3 V or external reference voltage (1.8 to 5.5 V) 200 MHz single data rate (SDR)
32 LVDS digital I/O channels
300 Mb/s double data rate (DDR)
10 PFI lines for triggering Up to 16 Mbits/s data rates
16 RS-485/RS-422 compatible channels
Half or Full Duplex
100 Ohm terminated 32 simultaneous 50 MS/s, 12-bit channels
Uses TI AFE5801 analog front end including variable gain amplifiers and ADCs
2 Vpp, 100 differential inputs with AC coupling
Built-in antialias filters and programmable time-variable gain control
16 digital outputs with per-channel phase control that can be coupled to pulser arrays
Ability to synchronize multiple devices for high-channel-count applications Dual 100 MS/s, 14-bit inputs
Dual 100 MS/s, 16-bit outputs
2 Vpp differential I/O (1 Vpp single-ended capable)
40 MHz bandwidth (-3 dB)
External clock input and output
8 general-purpose digital I/O lines
Full transcript